lh28f160bg-tl Sharp Microelectronics of the Americas, lh28f160bg-tl Datasheet - Page 14
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lh28f160bg-tl
Manufacturer Part Number
lh28f160bg-tl
Description
M-bit Smart Flash Memories
Manufacturer
Sharp Microelectronics of the Americas
Datasheet
1.LH28F160BG-TL.pdf
(36 pages)
The only other valid commands while block erase is
suspended are Read Status Register and Block
Erase Resume. After a Block Erase Resume
command is written to the flash memory, the WSM
will continue the block erase process. Status
register bits SR.6 and SR.7 will automatically clear
and RY/BY# will return to V
Resume
automatically outputs status register data when
read (see Fig. 5). V
same V
erase is suspended. RP# must also remain at V
or V
WP# must also remain at V
WP# level used for block erase). Block erase
cannot resume until word write operations initiated
during block erase suspend have completed.
4.8 Word Write Suspend Command
The Word Write Suspend command allows word
write interruption to read data in other flash memory
locations. Once the word write process starts,
writing the Word Write Suspend command requests
that the WSM suspend the word write sequence at
a predetermined point in the algorithm. The device
continues to output status register data when read
after the Word Write Suspend command is written.
Polling status register bits SR.7 and SR.2 can
determine when the word write operation has been
suspended (both will be set to "1"). RY/BY# will
also transition to high-impedance. Specification
t
At this point, a Read Array command can be written
to read data from location other than that which is
suspended. The only other valid commands while
word write is suspended are Read Status Register
and Word Write Resume. After Word Write Resume
command is written to the flash memory, the WSM
will continues the word write process. Status register
bits SR.2 and SR.7 will automatically clear and
RY/BY# will return to V
Resume
WHRH1
HH
(the same RP# level used for block erase).
defines the word write suspend latency.
PP
level used for block erase) while block
command
command
PP
must remain at V
is
is
OL
. After the Word Write
written,
written,
IL
OL
. After the Erase
or V
IH
the
the
(the same
PPH1/2
device
device
(the
IH
- 14 -
automatically outputs status register data when read
(see Fig. 6). V
V
suspend mode. RP# must also remain at V
V
must also remain at V
used for word write).
4.9 Block Locking
This Boot Block flash memory architecture features
two hardware-lockable boot blocks so that the
kernel code for the system can be kept secure
while other blocks are programmed or erased as
necessary.
4.9.1 V
The V
complete write protection of all blocks in the flash
device.
4.9.2 WP# = V
The lockable blocks are locked when WP# = V
any program or erase operation to a locked block
will result in an error, which will be reflected in the
status register. For top configuration, the top two
boot blocks are lockable. For the bottom
configuration, the bottom two boot blocks are
lockable. Unlocked blocks can be programmed or
erased normally (Unless V
4.9.3 BLOCK UNLOCKING
WP# = V
blocks.
These blocks can now be programmed or erased.
WP# or RP# controls all block locking and V
provides protection against spurious writes. Table 4
defines the write protection methods.
PP
HH
level used for word write) while in word write
(the same RP# level used for word write). WP#
PP
PP
programming voltage can be held low for
IH
= V
or RP# =V
PP
IL
IL
FOR COMPLETE PROTECTION
must remain at V
FOR BLOCK LOCKING
LH28F160BG-TL/BGH-TL
IL
or V
HH
PP
IH
is below V
unlocks all lockable
(the same WP# level
PPH1/2
PPLK
(the same
).
IH
PP
IL
or
;