lh28f160bg-tl Sharp Microelectronics of the Americas, lh28f160bg-tl Datasheet - Page 6
lh28f160bg-tl
Manufacturer Part Number
lh28f160bg-tl
Description
M-bit Smart Flash Memories
Manufacturer
Sharp Microelectronics of the Americas
Datasheet
1.LH28F160BG-TL.pdf
(36 pages)
of status (versus software polling) and status
masking (interrupt masking for background block
erase, for example). Status polling using RY/BY#
minimizes both CPU overhead and system power
consumption. When low, RY/BY# indicates that the
WSM is performing a block erase or word write.
RY/BY#-High-impedance indicates that the WSM is
ready for a new command, block erase is
suspended (and word write is inactive), word write
is suspended, or the device is in deep power-down
mode.
The access time is 100 ns or 120 ns (t
V
temperature range, 0 to +70°C (LH28F160BG-TL)/
–25 to +85°C (LH28F160BGH-TL).
CC
supply voltage range of 2.7 to 3.6 V over the
AVQV
) at the
- 6 -
The Automatic Power Saving (APS) feature
substantially reduces active current when the
device is in static mode (addresses not switching).
In APS mode, the typical I
2.7 V V
When CE# and RP# pins are at V
CMOS standby mode is enabled. When the RP#
pin is at GND, deep power-down mode is enabled
which minimizes power consumption and provides
write protection during reset. A reset time (t
required from RP# switching high until outputs are
valid. Likewise, the device has a wake time (t
from RP#-high until writes to the CUI are
recognized. With RP# at GND, the WSM is reset
and the status register is cleared.
CC
.
LH28F160BG-TL/BGH-TL
CCR
current is 3 mA at
CC
, the I
PHQV
PHEL
) is
CC
)