lh28f400su-nc Sharp Microelectronics of the Americas, lh28f400su-nc Datasheet - Page 8

• Manufacturer Part Number: lh28f400su-nc
• Description: 512k 256k Flash Memory
• Manufacturer: Sharp Microelectronics of the Americas

LH28F400SU-NC
LH28F008SA-Compatible Mode Command Bus Definitions
ADDRESS
AA = Array Address
BA = Block Address
IA = Identifier Address
WA = Write Address
X = Don’t Care
NOTES:
1. Following the intelligent identifier command, two Read operations access the manufacturer and device signature codes.
2. The CSR is automatically available after device enters Data Write, Erase or Suspend operations.
3. Clears CSR.3, CSR.4, and CSR.5. See Status register definitions.
4. While device performs Block Erase, if you issue Erase Suspend command (B0H), be sure to confirm ESS (Erase-Suspend-Status) is
LH28F400SU-NC Performance Enhancement Command Bus Definitions
ADDRESS
BA = Block Address
WA = Write Address
X = Don’t Care
NOTES:
1. After initial device power-up, or return from deep power-down mode, the block lock status bits default to the locked state independent of
2. To reflect the actual lock-bit status, the Protect Set/Confirm command must be written after Lock Block/Confirm command.
3. When Protect Reset/Confirm command is written, all blocks can be written and erased regardless of the state of the lock-bits.
4. The Lock Block/Confirm command must be written after Protect Reset/Confirm command was written.
5. A
6. Second bus cycle address of Protect Set/Confirm and Protect Reset/Confirm command is 0FFH. Specifically A
8
Protect Set/Confirm
Protect Reset/Confirm
Lock Block/Confirm
Erase All Unlocked
Blocks
Two-Byte Write
Read Array
Intelligent Identifier
Read Compatible Status Register
Clear Status Register
Word Write
Alternate Word Write
Block Erase/Confirm
Erase Suspend/Resume
set to 1 on compatible status register. In the case, ESS bit was not set to 1, also completed the Erase (ESS = 0, WSMS = 1), be sure
to issue Resume command (D0H) after completed next Erase command. Beside, when the Erase Suspend command is issued, while
the device is not in Erase, be sure to issue Resume command (D0H) after the next erase complete.
the data in the corresponding lock bits. In order to upload the lock bit status, it requires to write Protect Set/Confirm command.
WDL, A
others are don’t care.
1
is automatically complemented to load second byte of data. A
COMMAND
1
= 1 looks at the WDH. In word-wide (x16) mode A
COMMAND
MODE
DATA
ID = Identifier Data
WD = Write Data
DATA
AD = Array Data
WD (L, H) = Write Data (Low, High)
WD (H, L) = Write Data (High, Low)
AD = Array Data
CSRD = CSR Data
x8
OPER. ADD. DATA OPER. ADD.
Write
Write
Write
Write
Write
FIRST BUS CYCLE
OPER.
Write
Write
Write
Write
Write
Write
Write
Write
X
X
X
X
X
FIRST BUS CYCLE
A7H
FBH
57H
47H
77H
ADDRESS
1
, don't care.
X
X
X
X
X
X
X
X
Write
Write
Write
Write
Write
SECOND BUS CYCLE
1
value determines which WD is supplied first: A
0FFH
0FFH
DATA
FFH
50H
40H
10H
20H
B0H
90H
70H
BA
A
X
-1
WD (L, H) Write
DATA
D0H
D0H
D0H
D0H
4M (512K × 8, 256K × 16) Flash Memory
OPER.
Read
Read
Read
Write
Write
Write
Write
SECOND BUS CYCLE
OPER. ADD.
THIRD BUS CYCLE
ADDRESS
WA
WA
AA
BA
IA
X
X
WA
9
- A
WD (H, L) 1, 2, 5
1
= 0 looks at the
CSRD
DATA
DATA
8
D0H
D0H
WD
WD
AD
= 0, A
ID
7
- A
NOTE
1, 2, 4
NOTE
0
1, 2
1, 2
3
4
4
1
2
= 1,
3