cat34c02 Catalyst Semiconductor, cat34c02 Datasheet - Page 10

• Manufacturer Part Number: cat34c02
• Description: 2-kb I?c Eeprom For Ddr2 Dimm Serial Presence Detect
• Manufacturer: Catalyst Semiconductor

SOFTWARE WRITE PROTECTION
The lower half of memory (first 128 bytes) can be
protected against Write requests by setting one of two
Software Write Protection (SWP) flags.
The Permanent Software Write Protection (PSWP) flag
can be set or read while all address pins are at regular
CMOS levels (GND or V
voltage V
clear or read the Reversible Software Write Protection
(RSWP) flag. The D.C. OPERATING CONDITIONS for
RSWP operations are shown in Table 1.
The SWP commands are listed in Table 2. All commands
are preceded by a START and terminated with a STOP,
following the ACK or NoACK from the CAT34C02. All
SWP related Slave addresses use the pre-amble: 0110
(6h), instead of the regular 1010 (Ah) used for memory
access. For PSWP commands, the three address pins
can be at any logic level, whereas for RSWP commands
the address pins must be at pre-assigned logic levels.
V
established on pin A
just beyond the STOP. Otherwise an RSWP request could
be interpreted by the CAT34C02 as a PSWP request.
The SWP Slave addresses follow the standard I
convention, i.e. to read the state of the SWP flag, the
LSB of the Slave address must be ‘1’, and to set or clear
a flag, it must be ‘0’. For Write commands a dummy
byte address and dummy data byte must be provided
(Figure 12). In contrast to a regular memory Read, a
SWP Read does not return Data. Instead the CAT34C02
will respond with NoACK if the flag is set and with ACK if
the flag is not set. Therefore, the Master can immediately
follow up with a STOP, as there is no meaningful data
following the ACK interval (Figure 13).
TABLE 1: RSWP D.C. OPERATING CONDITIONS
(1) To prevent damaging the CAT34C02 while applying V
Doc. No. MD-1095, Rev. K
CAT34C02
HV
Symbol
ΔV
series resistor (> 1.5 kΩ) between the supply and the input pin. The resistance is only limited by the combination of V
I
As an example: V
I
V
HVD
is interpreted as logic ‘1’. The V
HVD
I
HV
HV
HV
. While the resistor can be omitted if V
HV
Parameter
A
A
A
A
must be present on address pin A
0
0
0
0
Overdrive (V
High Voltage Detector Current
Very High Voltage
Input Current @ V
CC
0
= 1.7 V, V
before the START and maintained
CC
HV
HV
), whereas the very high
= 8 V, 1.5 kΩ < R
- V
HV
HV
CC
condition must be
HV
)
is clamped well below 10 V, it nevertheless provides simple protection against EOS events.
S
< 15 kΩ.
HV
0
, it is strongly recommended to limit the power delivered to pin A
to set,
Test Conditions
1.7 V < V
(1)
2
C
10
CC
FFH
7FH
00H
HARDWARE WRITE PROTECTION
With the WP pin held HIGH, the entire memory, as well
as the SWP flags are protected against Write operations,
see Memory Protection Map below. If the WP pin is left
floating or is grounded, it has no impact on the operation
of the CAT34C02.
The state of the WP pin is strobed on the last falling
edge of SCL immediately preceding the first data byte
(Figure 8). If the WP pin is HIGH during the strobe inter-
val, the CAT34C02 will not acknowledge the data byte
and the Write request will be rejected.
< 3.6 V
Memory Protection Map
Min
4.8
7
Characteristics subject to change without notice
Hardware Write Protectable
(by connecting WP pin to
Vcc)
Software Write Protectable
(by setting the write
protect flags)
Max
0.1
10
© Catalyst Semiconductor, Inc.
1
HV
0
and maximum
, by inserting a
Units
mA
mA
V
V