hyb18t512161bf-33 Infineon Technologies Corporation, hyb18t512161bf-33 Datasheet - Page 18

• Manufacturer Part Number: hyb18t512161bf-33
• Description: 512-mbit X16 Gddr2 Dram
• Manufacturer: Infineon Technologies Corporation

3.2
Read and write accesses to the DDR2 SDRAM are
burst oriented; accesses start at a selected location
and continue for the burst length of four or eight in a
programmed sequence.
Accesses begin with the registration of an Activate
command, which is followed by a Read or Write
command. The address bits registered coincident with
the activate command are used to select the bank and
row to be accessed. BA[1:0] selects the bank, A[12:0]
selects the row for x16 components.
3.3
DDR2 SDRAM’s must be powered up and initialized in a predefined manner. Operational procedures other than
those specified may result in undefined operation.
Power-up and Initialization Sequence
The following sequence is required for POWER UP and Initialization.
1. Apply power and attempt to maintain CKE below
2. Start clock (CK, CK) and maintain stable power and
Figure 4
Data Sheet
0.2
may be undefined). To guarantee ODT off,
must be valid and a low level must be applied to the
ODT pin. Maximum power up interval for
is specified as 20.0 ms. The power interval is
defined as the amount of time it takes for
to power-up from 0 V to
two sets of conditions must be met:
–
converter output, AND
–
–
or
– Apply
Apply
Apply
V
clock condition for a minimum of 200 s.
REF
V
V
V
DD
TT
REF
.
,
V
is limited to
V
V
V
tracks
DDQ
DDL
DDQ
DDL
V
Basic Functionality
Power On and Initialization
Initialization Sequence after Power up
DD
and ODT at a low state (all other inputs
and
before or at the same time as
before or at the same time as
before or at the same time as
V
DDQ
V
DDQ
V
/2
DDQ
are driven from a single power
max/2, AND
V
DDQ
. At least one of these
V
V
DD
V
DD
V
V
DDQ.
V
TT
DDL.
/
/
REF
&
V
V
–
DDQ
DDQ
–
18
The address bits registered coincident with the Read or
Write command are used to select the starting column
location for the burst access and to determine if the
Auto-Precharge command is to be issued.
Prior to normal operation, the DDR2 SDRAM must be
initialized. The following sections provide detailed
information covering device initialization, register
definition, command description and device operation.
3. Apply NOP or Deselect commands and take CKE
4. Continue NOP or Deselect Commands for 400 ns,
5. Issue EMRS(2) command.
6. Issue EMRS(3) command.
7. Issue EMRS(1) command to enable DLL.
8. Issue a MRS command for “DLL reset”.
9. Issue Precharge-all command.
10. Issue 2 or more Auto-refresh commands.
11. Issue the final MRS command to turn the DLL on
12. At least 200 clocks after step 8, issue EMRS(1)
13. The DDR2 SDRAM is now ready for normal
512-Mbit Double-Data-Rate-Two SDRAM
high.
then issue a Precharge All command.
and to set the necessary operating parameter.
commands to either execute the OCD calibration or
select the OCD default. Issue the final EMRS(1)
command to exit OCD calibration mode and set the
necessary operating parameters.
operation.
HYB18T512161BF–22/25/28/33
Functional Description
05102005-C5U8-7TLE
Rev. 1.1, 2005-08