at45db021a ATMEL Corporation, at45db021a Datasheet - Page 3

• Manufacturer Part Number: at45db021a
• Description: 2-megabit 2.7-volt Only Serial Dataflash
• Manufacturer: ATMEL Corporation

Memory Architecture Diagram
Device Operation
The device operation is controlled by instructions from the
host processor. The list of instructions and their associated
opcodes are contained in Tables 1 through 4 (pages 8 and
9). A valid instruction starts with the falling edge of CS fol-
lowed by the appropriate 8-bit opcode and the desired
buffer or main memory address location. While the CS pin
is low, toggling the SCK pin controls the loading of the
opcode and the desired buffer or main memory address
location through the SI (serial input) pin. All instructions,
addresses, and data are transferred with the most signifi-
cant bit (MSB) first.
Buffer addressing is referenced in the datasheet using the
terminology BFA8 - BFA0 to denote the nine address bits
required to designate a byte address within a buffer. Main
memory addressing is referenced using the terminology
PA9 - PA0 and BA8 - BA0 where PA9 - PA0 denotes the
10 address bits required to designate a page address and
BA8-BA0 denotes the nine address bits required to desig-
nate a byte address within the page.
Read Commands
By specifying the appropriate opcode, data can be read
from the main memory or from either one of the two data
buffers. The DataFlash supports two categories of read
modes in relation to the SCK signal. The differences
between the modes are in respect to the inactive state of
the SCK signal as well as which clock cycle data will begin
to be output. The two categories, which are comprised of
four modes total, are defined as Inactive Clock Polarity Low
SECTOR ARCHITECTURE
135,168 bytes (128K + 4K)
65,472 bytes (62K + 1984)
67,584 bytes (64K + 2K)
SECTOR 1 = 248 Pages
SECTOR 2 = 256 Pages
SECTOR 3 = 512 Pages
SECTOR 0 = 8 Pages
2112 bytes (2K + 64)
SECTOR 0
BLOCK ARCHITECTURE
Block = 2112 bytes
BLOCK 126
BLOCK 127
BLOCK 30
BLOCK 31
BLOCK 32
BLOCK 33
BLOCK 62
BLOCK 63
BLOCK 64
BLOCK 65
BLOCK 0
BLOCK 1
BLOCK 2
(2K + 64)
or Inactive Clock Polarity High and SPI Mode 0 or SPI
Mode 3. A separate opcode (refer to Table 1 on page 8 for
a complete list) is used to select which category will be
used for reading. Please refer to the “Detailed Bit-level
Read Timing” diagrams in this datasheet for details on the
clock cycle sequences for each mode.
CONTINUOUS ARRAY READ: By supplying an initial
starting address for the main memory array, the Continu-
ous Array Read command can be utilized to sequentially
read a continuous stream of data from the device by simply
providing a clock signal; no additional addressing informa-
tion or control signals need to be provided. The DataFlash
incorporates an internal address counter that will automati-
cally increment on every clock cycle, allowing one
continuous read operation without the need of additional
address sequences. To perform a continuous read, an
opcode of 68H or E8H must be clocked into the device fol-
lowed by 24 address bits and 32 don’t care bits. The first
five bits of the 24-bit address sequence are reserved for
upward and downward compatibility to larger and smaller
density devices (see Notes under “Command Sequence for
Read/Write Operations” diagram). The next 10 address bits
(PA9 -PA0) specify which page of the main memory array
to read, and the last nine bits (BA8 - BA0) of the 24-bit
address sequence specify the starting byte address within
the page. The 32 don’t care bits that follow the 24 address
bits are needed to initialize the read operation. Following
the 32 don’t care bits, additional clock pulses on the SCK
pin will result in serial data being output on the SO (serial
output) pin.
8 Pages
PAGE ARCHITECTURE
Page = 264 bytes
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PAGE 0
PAGE 1
PAGE 6
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PAGE 8
PAGE 9
(256 + 8)
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