s-93c46b Seiko Instruments Inc., s-93c46b Datasheet - Page 12

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s-93c46b

Manufacturer Part Number
s-93c46b
Description
Cmos Serial E2prom
Manufacturer
Seiko Instruments Inc.
Datasheet

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12
CMOS SERIAL E
S-93C46B/56B/66B
Operation
Start Bit
All instructions are executed by inputting DI in synchronization with the rising edge of SK after CS goes
high. An instruction set is input in the order of start bit, instruction, address, and data.
A start bit is recognized when the DI pin goes high at the rise of SK after CS goes high. After CS goes high,
a start bit is not recognized even if the SK pulse is input as long as the DI pin is low.
1. Dummy clock
2. Start bit input failure
Instruction input finishes when CS goes low. A low level must be input to CS between commands during
t
inputs are invalid and no instructions are allowed.
CDS
SK clocks input while the DI pin is low before a start bit is input are called dummy clocks. Dummy
clocks are effective when aligning the number of instruction sets (clocks) sent by the CPU with those
required for serial memory operation. For example, when a CPU instruction set is 16 bits, the number
of instruction set clocks can be adjusted by inserting a 7-bit dummy clock for the S-93C46B and a 5-bit
dummy clock for the S-93C56B/66B.
• When the output status of the DO pin is high during the verify period after a write operation, if a high
• When a 3-wire interface is configured by connecting the DI input pin and DO output pin, a period in
. While a low level is being input to CS, the S-93C46B/56B/66B is in standby mode, so the SK and DI
level is input to the DI pin at the rising edge of SK, the S-93C46B/56B/66B recognizes that a start bit
has been input. To prevent this failure, input a low level to the DI pin during the verify operation
period (refer to “4.1 Verify operation”).
which the data output from the CPU and the serial memory collide may be generated, preventing
successful input of the start bit.
Connection between DI and DO)”.
2
PROM
Seiko Instruments Inc.
Take the measures described in “
3-Wire Interface (Direct
Rev.4.3
_00

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