stk16c88-45i Simtek Corporation, stk16c88-45i Datasheet - Page 9

• Manufacturer Part Number: stk16c88-45i
• Description: 32kx8 Autostore+ Nvsram
• Manufacturer: Simtek Corporation

Document Control #ML0018 Rev 2.0
The software sequence must be clocked with E
controlled
Once the sixth address in the sequence has been
entered, the
chip will be disabled. It is important that
cycles and not
sequence, although it is not necessary that G be
low for the sequence to be valid. After the t
cycle time has been fulfilled, the
activated for
SOFTWARE NONVOLATILE RECALL
A software
sequence of
the software
cycle, the following sequence of
must be performed:
Internally,
the
tile information is transferred into the
After the t
be ready for
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
SRAM
Jan, 2008
100
80
60
40
20
0
RECALL
data is cleared, and second, the nonvola-
READ
RECALL
READ
STORE
READ
STORE
Figure 2: I
RECALL
READ
cycle time the
50
s.
WRITE
operations in a manner similar to
and
is a two-step procedure. First,
0E38 (hex)
31C7 (hex)
03E0 (hex)
3C1F (hex)
303F (hex)
0FC0 (hex)
initiation. To initiate the
0E38 (hex)
31C7 (hex)
03E0 (hex)
3C1F (hex)
303F (hex)
0C63 (hex)
cycle will commence and the
Cycle Time (ns)
and
100
CC
WRITE
cycle is initiated with a
(max) Reads
cycles be used in the
WRITE
150
SRAM
operation.
SRAM
TTL
CMOS
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate STORE cycle
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate RECALL cycle
READ
operations. The
will once again
200
will again be
SRAM
operations
RECALL
READ
cells.
STORE
9
RECALL
non-volatile storage elements. The nonvolatile data
can be recalled an unlimited number of times.
HARDWARE PROTECT
The STK16C88 offers hardware protection against
inadvertent
during low-voltage conditions. When V
all software
are inhibited.
LOW AVERAGE ACTIVE POWER
The STK16C88 draws significantly less current
when it is cycled at times longer than 50ns. Figure 2
shows the relationship between I
time. Worst-case current consumption is shown for
both
perature range, V
enable). Figure 3 shows the same relationship for
WRITE
than 100%, only standby current is drawn when the
chip is disabled. The overall average current drawn
by the STK16C88 depends on the following items:
1)
chip enable; 3) the overall cycle rate for accesses;
4) the ratio of
temperature; 6) the V
CMOS
CMOS
100
80
60
40
20
cycles. If the chip enable duty cycle is less
0
operation in no way alters the data in the
vs.
and
STORE
STORE
Figure 3: I
TTL
READs
50
TTL
CC
input levels; 2) the duty cycle of
=5.5V, 100% duty cycle on chip
operation and
operations and
input levels (commercial tem-
CC
Cycle Time (ns)
CC
to
100
level; and 7) I/O loading.
(max) Writes
WRITEs
150
TTL
CC
CMOS
; 5) the operating
and
SRAM WRITE
SRAM WRITE
STK16C88
200
CC
READ
< V
SWITCH
cycle
s
s
,