psd4235g2 STMicroelectronics, psd4235g2 Datasheet - Page 99

• Manufacturer Part Number: psd4235g2
• Description: Flash In-system Programmable Isp Peripherals For 16-bit Mcus 5v Supply
• Manufacturer: STMicroelectronics

PSD4235G2
22
22.1
22.2
22.3
22.4
Table 51.
MCU I/O
PLD output
Address Out
Data Port
Peripheral I/O
PMMR0 and PMMR2
Port configuration
Power-on Reset, Warm Reset and Power-down
Power-on Reset
Upon Power-up, the PSD requires a Reset (RESET) pulse of duration t
1 ms) after V
some of the registers and sets the Flash memory into Operating mode. After the rising edge
of Reset (RESET), the PSD remains in the Reset mode for an additional period, t
(maximum 120 ns), before the first memory access is allowed.
The PSD Flash memory is reset to the READ mode upon Power-up. Sector Select (FS0-
FS7 and CSBOOT0-CSBOOT3) must all be low, Write Strobe (WR/WRL, CNTL0) high,
during Power-on Reset for maximum security of the data contents and to remove the
possibility of data being written on the first edge of Write Strobe (WR/WRL, CNTL0). Any
Flash memory WRITE cycle initiation is prevented automatically when V
Warm Reset
Once the device is up and running, the device can be reset with a pulse of a much shorter
duration, t
operational after warm reset.
I/O pin, register and PLD status at Reset
Table 51
Power-down mode. PLD outputs are always valid during warm reset, and they are valid in
Power-on Reset once the internal PSD Configuration bits are loaded. This loading of PSD is
completed typically long before the V
the state of the outputs are determined by equations specified in PSDsoft Express.
Reset of Flash Memory Erase and Program cycles
An external Reset (RESET) also resets the internal Flash memory state machine. During a
Flash memory Program or Erase cycle, Reset (RESET) terminates the cycle and returns the
Flash memory to the READ mode within a period of t
Status During Power-On Reset, Warm Reset and Power-down mode
shows the I/O pin, register and PLD status during Power-on reset, warm reset and
NLNH
CC
Input mode
Valid after internal PSD
configuration bits are
loaded
Tri-stated
Tri-stated
Tri-stated
Cleared to ’0’
(minimum 150 ns). The same t
is steady. During this period, the device loads internal configurations, clears
Power-On Reset
Figure 33
CC
shows the timing of the Power-up and warm reset.
ramps up to operating level. Once the PLD is active,
Input mode
Valid
Tri-stated
Tri-stated
Tri-stated
Unchanged
Power-on Reset, Warm Reset and Power-down
OPR
Warm Reset
period is needed before the device is
NLNH-A
(minimum 25 μs).
Unchanged
Depends on inputs to PLD
(addresses are blocked in
PD mode)
Not defined
Tri-stated
Tri-stated
Unchanged
Power-down mode
NLNH-PO
CC
is below V
(minimum
OPR
99/129
LKO
.