m59dr032ea STMicroelectronics, m59dr032ea Datasheet
m59dr032ea
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m59dr032ea Summary of contents
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... PROGRAM/ERASE CYCLES per BLOCK 20 YEARS DATA RETENTION – Defectivity below 1ppm/year ELECTRONIC SIGNATURE – Manufacturer Code: 0020h – Top Device Code, M59DR032EA: 00A0h – Bottom Device Code, M59DR032EB: 00A1h April 2003 32 Mbit (2Mb x 16, Dual Bank, Page ) 1.8V Supply Flash Memory Figure 1. Packages ...
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... M59DR032EA, M59DR032EB TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3. TFBGA Connections (Top view through package Table 2. Bank Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 4. Security Block and Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Address Inputs (A0-A20 Data Input/Output (DQ0-DQ15 Chip Enable (E Output Enable (G Write Enable (W) ...
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... Table 15. Capacitance Table 16. DC Characteristics Figure 7. Random Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 8. Page Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 17. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 9. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 18. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 10. Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 19. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 M59DR032EA, M59DR032EB 3/43 ...
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... Table 24. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 25. Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 APPENDIX A. BLOCK ADDRESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 26. Bank A, Top Boot Block Addresses M59DR032EA Table 27. Bank B, Top Boot Block Addresses M59DR032EA Table 28. Bank B, Bottom Boot Block Addresses M59DR032EB . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 29. Bank A, Bottom Boot Block Addresses M59DR032EB . . . . . . . . . . . . . . . . . . . . . . . . . . 38 APPENDIX B. COMMON FLASH INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 30 ...
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... Table 2, and the Block Addresses are shown in Appendix A. The Parameter Blocks are located at the top of the memory address space for the M59DR032EA, and at the bottom for the M59DR032EB. Each block can be erased separately. Erase can be suspended, in order to perform either read or program in any other block, and then resumed ...
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... M59DR032EA, M59DR032EB Figure 3. TFBGA Connections (Top view through package A13 B A14 C A15 D A16 E V DDQ Table 2. Bank Organization Bank A Bank B 6/ A11 A18 A10 W A12 A9 NC A20 DQ11 DQ2 DQ14 DQ5 DQ12 DQ15 DQ6 DQ3 ...
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... Figure 4. Security Block and Protection Register Memory Map SECURITY BLOCK Parameter Block # 0 M59DR032EA, M59DR032EB PROTECTION REGISTER 88h User Programmable OTP 85h 84h Unique device number 81h Protection Register Lock 80h AI06185 7/43 ...
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... M59DR032EA, M59DR032EB SIGNAL DESCRIPTIONS See Figure 2, Logic Diagram, and Table 1, Signal Names, for a brief overview of the signals connect this device. Address Inputs (A0-A20). The Address Inputs select the cells in the memory array to access dur- ing Bus Read operations. During Bus Write opera- tions they control the commands sent to the Command Interface of the internal state machine ...
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... M59DR032EA, M59DR032EB and the P/E.C. is idle. The pow The power consumption DQ15-DQ0 V V Data Output Data Input Hi-Z IH ...
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... M59DR032EA, M59DR032EB COMMAND INTERFACE All Bus Write operations to the memory are inter- preted by the Command Interface. Commands consist of one or more sequential Bus Write oper- ations. An internal Program/Erase Controller han- dles all timings and verifies the correct execution of the Program and Erase commands. Two bus write cycles are required to unlock the Command Interface ...
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... Mode command). It uses the same sequence of cycles as the Quadruple Word Program command with the exception of the unlock cycles. M59DR032EA, M59DR032EB Block Lock Command. The Block Lock com- mand is used to lock a block and prevent Program or Erase operations from changing the data in it. ...
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... M59DR032EA, M59DR032EB Block Erase Command. The Block Erase com- mand can be used to erase a block. It sets all the bits within the selected block to ’1’. All previous data in the block is lost. If the block is protected then the Erase operation will abort, the data in the block will not be changed and the device will return to Read Array mode ...
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... Resume Erase. Read Data Polling or Toggle Bits until Erase completes or Erase is 30h suspended another time AAh 2AAh 55h PA C0h PA M59DR032EA, M59DR032EB 4th 5th 6th Read Memory Array until a new write cycle is initiated. Read Protection Register, Block Protection or command is issued. ...
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... M59DR032EA, M59DR032EB Table 5. Read Electronic Signature Code Device Manufacturer Code M59DR032EA Device Code M59DR032EB Note Don’t care. Table 6. Read Block Protection Block Status Locked Block IL IL Unlocked Block Locked-Down Block Note Don’t care. ...
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... ID data X 84h ID data X 85h OTP data X 86h OTP data X 87h OTP data X 88h OTP data Min (1) = 12V) 100,000 M59DR032EA, M59DR032EB DQ7-3 DQ2 DQ1 Security OTP 00000b prot.data prot.data ID data ID data ID data ID data ID data ID data ID data ID data ID data ID data ID data ID data ...
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... M59DR032EA, M59DR032EB BLOCK LOCKING The M59DR032E features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. This locking scheme has two levels of protection. Lock/Unlock - this first level allows software- only control of block locking. Lock-Down - this second level requires hardware interaction before locking can be changed ...
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... All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status transition locked block will restore the previous DQ0 value, giving a 111 or 110. IH Next Protection Status (WP, DQ1, DQ0) After After Block Lock Block Unlock Command Command 1,0,1 1,0,0 1,0,1 1,0,0 1,1,1 1,1,0 1,1,1 1,1,0 0,0,1 0,0,0 0,0,1 0,0,0 0,1,1 0,1,1 and M59DR032EA, M59DR032EB (1) After Block After Lock-Down WP transition Command 1,1,1 0,0,0 1,1,1 0,0,1 1,1,1 0,1,1 1,1,1 0,1,1 0,1,1 1,0,0 0,1,1 1,0,1 0,1,1 1,1,1 or 1,1,0 17/43 (3) ...
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... M59DR032EA, M59DR032EB STATUS REGISTER The Status Register provides information on the current or previous Program or Erase operations. Bus Read operations from any address within the bank, always read the Status Register during Pro- gram and Erase operations. The various bits convey information about the sta- tus and any errors of the operation ...
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... Erase Error due to the currently addressed block (when DQ5 = ’1’). Program in progress or Erase complete. Erase Suspend read on non Erase Suspend block. M59DR032EA, M59DR032EB Note Indicates the P/E.C. status, check during Program or Erase, and on completion before checking bits DQ5 for Program or Erase success. Successive reads output ...
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... M59DR032EA, M59DR032EB MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause per- manent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not im- Table 13 ...
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... OUT Note: Sampled only, not 100% tested. M59DR032EA, M59DR032EB Conditions summarized in Table 14, Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the operating conditions when rely- ing on the quoted parameters. M59DR032EA, M59DR032EB 85 100 Min Max Min 1.8 2.2 1 ...
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... M59DR032EA, M59DR032EB Table 16. DC Characteristics Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO Supply Current I CC1 (Read Mode) Supply Current I CC2 (Power-Down) I Supply Current (Standby) CC3 Supply Current (1) I CC4 (Program or Erase) Supply Current (1) I CC5 (Dual Bank) V Supply Current ...
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... Figure 7. Random Read AC Waveforms M59DR032EA, M59DR032EB 23/43 ...
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... M59DR032EA, M59DR032EB Figure 8. Page Read AC Waveforms 24/43 ...
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... after the falling edge of E without increasing t GLQV M59DR032EA, M59DR032EB M59DR032E 85 100 120 Max Min Max Min 100 120 85 100 100 ...
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... M59DR032EA, M59DR032EB Figure 9. Write AC Waveforms, Write Enable Controlled A0-A20 DQ0-DQ15 V DD tVDHEL Note: Addresses are latched on the falling edge of W, Data is latched on the rising edge of W Table 18. Write AC Characteristics, Write Enable Controlled Symbol Alt t t Address Valid to Next Address Valid ...
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... RP Low to Reset Complete During t PLQ7V Program/Erase tAVAV VALID tAVEL tWLEL tGHEL tELEH tDVEH Parameter Min M59DR032EA, M59DR032EB tELAX tEHWH tEHGL tEHEL tEHDX VALID M59DR032E 85 100 Max Min Max Min 100 120 ...
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... M59DR032EA, M59DR032EB Figure 11. Reset/Power-Down AC Waveform W DQ7 RP tPHQ7V Table 20. Reset/Power-Down AC Characteristics Symbol Alt Parameter RP High to Data Valid t PHQ7V1 (Read Mode) RP High to Data Valid t PHQ7V2 (Power-Down enabled Low to Reset Complete PLQ7V Pulse Width PLPH RP 28/43 READ VALID Test Condition During Program During Erase ...
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... Figure 12. Data Polling DQ7 AC Waveforms M59DR032EA, M59DR032EB 29/43 ...
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... M59DR032EA, M59DR032EB Figure 13. Data Toggle DQ6, DQ2 AC Waveforms 30/43 ...
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... START READ DQ5 & DQ7 at VALID ADDRESS DQ7 YES = DATA NO NO DQ5 = 1 YES READ DQ7 DQ7 YES = DATA NO FAIL Parameter Figure 15. Data Toggle Flowchart PASS AI06197 M59DR032EA, M59DR032EB M59DR032E Unit Min Max 8 100 0 100 0 100 0 100 0.8 4 START READ DQ5 & ...
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... M59DR032EA, M59DR032EB PACKAGE MECHANICAL Figure 16. TFBGA48 7x12mm - 8x6 ball array, 0.75 mm pitch, Package Outline BALL "A1" A Note: Drawing is not to scale. Table 22. TFBGA48 7x12mm - 8x6 ball array, 0.75 mm pitch, Package Mechanical Data Symbol Typ A A1 0.300 7.000 D1 5.250 ddd E 12.000 E1 3 ...
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... M59DR032EA, M59DR032EB ddd A2 A1 BGA-Z09 inches Typ Min 0.0079 0.0315 0.0157 0.0138 0.2756 0.2717 0.2067 – 0.2756 0.2717 0.1476 – 0.0295 – ...
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... M59DR032EA, M59DR032EB Figure 18. TFBGA48 Daisy Chain - Package Connections (Top view through package Figure 19. TFBGA48 Daisy Chain - PCB Connection Proposal (Top view through package 34/ AI03079 START POINT END POINT ...
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... Package ZB = TFBGA48 12mm, 0.75mm pitch ZF = TFBGA48 7mm, 0.75mm pitch Temperature Range 70° –40 to 85°C Option blank = Standard Packing T = Tape & Reel packing E = Lead-Free Package, Standard Packing F = Lead-Free Package, Tape & Reel Packing M59DR032EA, M59DR032EB M59DR032EA 35/43 ...
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... M59DR032EA, M59DR032EB Table 25. Daisy Chain Ordering Scheme Example: Device Type M59DR032E Daisy Chain ZB = TFBGA48: 7x12mm, 0.75mm pitch ZF = TFBGA48 7mm, 0.75mm pitch Option blank = Standard Packing T = Tape & Reel packing E = Lead-Free Package, Standard Packing F = Lead-Free Package, Tape & Reel Packing Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available op- tions (Speed, Package, etc ...
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... M59DR032EA, M59DR032EB 38 32 130000h-137FFFh 37 32 128000h-12FFFFh 36 32 120000h-127FFFh 35 32 118000h-11FFFFh 34 32 110000h-117FFFh 33 32 108000h-10FFFFh 32 32 100000h-107FFFh 31 32 0F8000h-0FFFFFh 30 32 0F0000h-0F7FFFh 29 32 ...
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... M59DR032EA, M59DR032EB Table 28. Bank B, Bottom Boot Block Addresses M59DR032EB Size # Address Range (KWord 1F8000h-1FFFFFh 54 32 1F0000h-1F7FFFh 53 32 1E8000h-1EFFFFh 52 32 1E0000h-1E7FFFh 51 32 1D8000h-1DFFFFh 50 32 1D0000h-1D7FFFh 49 32 1C8000h-1CFFFFh 48 32 1C0000h-1C7FFFh 47 32 1B8000h-1BFFFFh 46 32 1B0000h-1B7FFFh 45 32 1A8000h-1AFFFFh 44 32 1A0000h-1A7FFFh 43 32 198000h-19FFFFh 42 32 190000h-197FFFh ...
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... Address for Primary Algorithm extended Query table Alternate Vendor Command Set and Control Interface ID Code second vendor - specified algorithm supported (note: 0000h means none exists) Address for Alternate Algorithm extended Query table note: 0000h means none exists M59DR032EA, M59DR032EB Description 39/43 ...
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... M59DR032EA, M59DR032EB Table 32. CFI Query System Interface Information Offset Data V Logic Supply Minimum Program/Erase or Write voltage DD 1Bh 0017h V Logic Supply Maximum Program/Erase or Write voltage DD 1Ch 0022h V [Programming] Supply Minimum Program/Erase voltage PP 1Dh 0000h V [Programming] Supply Maximum Program/Erase voltage PP 1Eh 00C0h Typical timeout per single byte/word program (multi-byte program count = 1), 2 ...
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... Table 33. Device Geometry Definition Offset Word Data Mode 27h 0016h 28h 0001h 29h 0000h 2Ah 0000h 2Bh 0000h 2Ch 0002h M59DR032EA M59DR032EA Erase Block Region Information 2Dh 003Eh 2Eh 0000h 2Fh 0000h 30h 0001h 31h 0007h 32h 0000h 33h 0020h 34h 0000h ...
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... M59DR032EA, M59DR032EB REVISION HISTORY Table 34. Document Revision History Date Version 05-Feb-2002 -01 First Issue Document classified as Preliminary Data. Top and Bottom Device Codes modified, Program commands text clarified, Table 4, Commands modified, Table 9, Program and 04-Apr-2002 -02 Erase Times modified, Status Register Error bit DQ5 text clarified, Table 21, Data Polling and Toggle Bits AC Characteristics modified ...
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