m59dr032ea STMicroelectronics, m59dr032ea Datasheet - Page 9

• Manufacturer Part Number: m59dr032ea
• Description: 32 Mbit 2mb X 16, Dual Bank, Page 1.8v Supply Flash Memory
• Manufacturer: STMicroelectronics

BUS OPERATIONS
The following operations can be performed using
the appropriate bus cycles: Read Array (Random,
and Page Modes), Write, Output Disable, Standby
and Reset/Power-Down, see Table 3.
Read. Read operations are used to output the
contents of the Memory Array, the Electronic Sig-
nature, the Status Register, the CFI, the Block
Protection Status or the Configuration Register
status. Read operation of the memory array is per-
formed in asynchronous page mode, that provides
fast access time. Data is internally read and stored
in a page buffer. The page has a size of 4 words
and is addressed by A0-A1 address inputs. Read
operations of the Electronic Signature, the Status
Register, the CFI, the Block Protection Status, the
Configuration Register status and the Security
Code are performed as single asynchronous read
cycles (Random Read). Both Chip Enable E and
Output Enable G must be at V
output of the memory.
Write. Write operations are used to give com-
mands to the memory or to latch Input Data to be
programmed. A write operation is initiated when
Chip Enable E and Write Enable W are at V
Output Enable G at V
the falling edge of W or E whichever occurs last.
Commands and Input Data are latched on the ris-
ing edge of W or E whichever occurs first. Noise
pulses of less than 5ns typical on E, W and G sig-
nals do not start a write cycle.
Table 3. Bus Operations
Note: X = Don’t care.
Read
Write
Output Disable
Standby
Reset / Power-Down
Operation
IH
. Addresses are latched on
V
V
V
V
IL
E
X
IH
IL
IL
IL
in order to read the
V
V
V
G
X
X
IL
IH
IH
IL
with
Output Disable. The data outputs are high im-
pedance when the Output Enable G is at V
Write Enable W at V
Standby. The memory is in standby when Chip
Enable E is at V
er consumption is reduced to the standby level
and the outputs are high impedance, independent
of the Output Enable G or Write Enable W inputs.
Automatic Standby. In Read mode, after 150ns
of bus inactivity and when CMOS levels are driving
the addresses, the chip automatically enters a
pseudo-standby mode where consumption is re-
duced to the CMOS standby value, while outputs
still drive the bus.
Power-Down. The memory is in Power-Down
when the Configuration Register is set for Power-
Down and RP is at V
reduced to the Power-Down level, and Outputs are
in high impedance, independent of the Chip En-
able E, Output Enable G or Write Enable W inputs.
Dual Bank Operations. The Dual Bank allows
data to be read from one bank of memory while a
program or erase operation is in progress in the
other bank of the memory. Read and Write cycles
can be initiated for simultaneous operations in dif-
ferent banks without any delay. Status Register
during Program or Erase must be monitored using
an address within the bank being modified.
V
V
V
W
X
X
IH
IH
IL
RP
V
V
V
V
V
M59DR032EA, M59DR032EB
IH
IH
IH
IH
IH
IL
and the P/E.C. is idle. The pow-
IH
IL
.
. The power consumption is
WP
V
V
V
V
V
IH
IH
IH
IH
IH
Data Output
DQ15-DQ0
Data Input
Hi-Z
Hi-Z
Hi-Z
IH
with
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