tc58dvm92a5baj3 TOSHIBA Semiconductor CORPORATION, tc58dvm92a5baj3 Datasheet - Page 33

• Manufacturer Part Number: tc58dvm92a5baj3
• Description: 512-mbit 64m ? 8 Bits Cmos Nand E Prom Description
• Manufacturer: TOSHIBA Semiconductor CORPORATION

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Write/Erase Endurance
Data Retention
Read Disturb
(between block erases), a tiny charge may build up and can cause a cell to be soft programmed to another
state. After block erasure and reprogramming, the block may become usable again.
A read operation may disturb the data in memory. The data may change due to charge gain. Usually, bit
errors occur on other pages in the block, not the page being read. After a large number of read cycles
Write/Erase endurance failures may occur in a cell, page, or block, and are detected by doing a status read
after either an auto program or auto block erase operation. The cumulative bad block count will increase
along with the number of write/erase cycles.
The data in memory may change after a certain amount of storage time. This is due to charge loss or charge
gain. After block erasure and reprogramming, the block may become usable again.
Here is the combined characteristics image of Write/Erase Endurance and Data Retention.
Retention
This reliability guidance is intended to notify some guidance related to using NAND flash with
1 bit ECC for each 512 bytes. For detailed reliability data, please refer to TOSHIBA’s reliability note.
Although random bit errors may occur during use, it does not necessarily mean that a block is bad.
Generally, a block should be marked as bad when a program status failure or erase status failure is detected.
The other failure modes may be recovered by a block erase.
ECC treatment for read data is mandatory due to the following Data Retention and Read Disturb failures.
[Years]
Reliability Guidance
Data
Write/Erase Endurance [Cyc les]
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TC58DVM92A5BAJ3
2010-06-16