xcf32pvo48m Xilinx Corp., xcf32pvo48m Datasheet - Page 11

• Manufacturer Part Number: xcf32pvo48m
• Description: < B L Qpro Extended Temperature Platform Flash In-system Programmable Configuration Prom
• Manufacturer: Xilinx Corp.

•
FPGA SelectMAP (Parallel) Device Chaining
Multiple Virtex-II FPGAs can be configured using the
SelectMAP mode, and be made to start up simultaneously.
To configure multiple devices in this way, wire the individual
CCLK, DONE, INIT, Data ([D0..D7]), Write (WRITE or
RDWR_B), and BUSY pins of all the devices in parallel. If all
devices are to be configured with the same bitstream,
readback is not being used, and the CCLK frequency
selected does not require the use of the BUSY signal, the
CS_B pins can be connected to a common line so all of the
devices are configured simultaneously
With additional control logic, the individual devices can be
loaded separately by asserting the CS_B pin of each device
in turn and then enabling the appropriate configuration data.
The PROM can also store the individual bitstreams for each
FPGA for SelectMAP configuration in separate design
revisions. When design revisioning is utilized, additional
control logic can be used to select the appropriate bitstream
by asserting the EN_EXT_SEL pin, and using the
REV_SEL[1:0] pins to select the required bitstream, while
asserting the CS_B pin for the FPGA the bitstream is
targeting
For clocking the parallel configuration chain, either the first
FPGA in the chain can be set to Master SelectMAP,
generating the CCLK, with the remaining devices set to
Slave SelectMAP, or all the FPGA devices can be set to
Slave SelectMAP and an externally generated clock can be
used to drive the configuration interface. Again, the
respective device data sheets should be consulted for
detailed information on a particular FPGA device, including
which configuration modes are supported by the targeted
FPGA device.
Cascading Configuration PROMs
When configuring multiple FPGAs in a serial daisy chain,
configuring multiple FPGAs in a SelectMAP parallel chain,
or configuring a single FPGA requiring a larger
configuration bitstream, cascaded PROMs provide
additional memory
Figure 11, page
Platform Flash PROMs can be concatenated by using the
CEO output to drive the CE input of the downstream device.
The clock signal and the data outputs of all Platform Flash
PROMs in the chain are interconnected. After the last data
DS541 (v1.0) November 27, 2006
Product Specification
The PROM CF pin is typically connected to the FPGA's
PROG_B (or PROGRAM) input. For the XQF32P only,
the CF pin is a bidirectional pin. If the XQF32P CF pin
is not connected to the FPGA's PROG_B (or
PROGRAM) input, then the pin should be tied High.
(Figure 12, page
R
18, and
(Figure 7, page
Figure 12, page
QPro Extended Temperature Platform Flash In-System Programmable Configuration PROM
19).
14,
(Figure 9, page
Figure 10, page
19). Multiple
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16).
17,
from the first PROM is read, the first PROM asserts its CEO
output Low and drives its outputs to a high-impedance
state. The second PROM recognizes the Low level on its CE
input and immediately enables its outputs.
After configuration is complete, address counters of all
cascaded PROMs are reset if the PROM OE/RESET pin
goes Low or CE goes High.
When utilizing the advanced features for the XQF32P
Platform Flash PROM, including the clock output (CLKOUT)
option, decompression option, or design revisioning,
programming files which span cascaded PROM devices
can only be created for cascaded chains containing only
XQF32P PROM.
Initiating FPGA Configuration
The options for initiating FPGA configuration via the
Platform Flash PROM include:
•
•
•
Following the FPGA’s power-on sequence or the assertion
of the PROG_B (or PROGRAM) pin the FPGA’s
configuration memory is cleared, the configuration mode is
selected, and the FPGA is ready to accept a new
configuration bitstream. The FPGA’s PROG_B pin can be
controlled by an external source, or alternatively, the
Platform Flash PROMs incorporate a CF pin that can be
tied to the FPGA’s PROG_B pin. Executing the CONFIG
instruction through JTAG pulses the CF output Low once for
300-500 ns, resetting the FPGA and initiating configuration.
The iMPACT software can issue the JTAG CONFIG
command to initiate FPGA configuration by setting the
"Load FPGA" option.
When using the XQF32P Platform Flash PROM with design
revisioning enabled, the CF pin should always be connected
to the PROG_B (or PROGRAM) pin on the FPGA to ensure
that the current design revision selection is sampled when
the FPGA is reset. The XQF32P PROM samples the current
design revision selection from the external REV_SEL pins
or the internal programmable Revision Select bits on the
rising edge of CF. When the JTAG CONFIG command is
executed, the XQF32P samples the new design revision
selection before initiating the FPGA configuration
sequence. When using the XQF32P Platform Flash PROM
without design revisioning, if the CF pin is not connected to
the FPGA PROG_B (or PROGRAM) pin, then the XQF32P
CF pin must be tied High.
Automatic configuration on power up
Applying an external PROG_B (or PROGRAM) pulse
Applying the JTAG CONFIG instruction
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