ncp1239f ON Semiconductor, ncp1239f Datasheet - Page 17

• Manufacturer Part Number: ncp1239f
• Description: Lowstandby High Performance Pwm Controller
• Manufacturer: ON Semiconductor

Startup Sequence
outlet, the internal current source (typically 3.6 mA) is
biased and charges up the V
on this V
16.4 V), the current source turns off and no longer wastes
any power. At this time, the energy stored by the V
capacitor serves to supply the controller and the auxiliary
supply is supposed to take over before V
V
structure:
The current source brings V
CCOFF
16.4 V /
11.2 V
When the power supply is first connected to the mains
Pin 10 monitors the power switch current and compares it to the current setpoint (one third of the feedback voltage). The
current setpoint is limited by the soft−start during the power−on sequence and permanently clamped to 0.9 V In the
NCP1239F, a second pin (Pin 9) monitors the current to clamp the power.
CLK
R
S
. Figure 35 shows the internal arrangement of this
CC
Q
Q
Current Sense
Comparator
capacitor reaches the V
Over Power
Comparator
+
−
−
+
+
−
Figure 35.
CC
+
500 mV
CC
16
13
10
above 16.4 V and then turns off
LEB
LEB
20k
3.6 mA/0
capacitor. When the voltage
Vdd
/ 3
CCON
0.9 V
CV
HV
CC
Ramp Compensation
Overcurrents Compensation
CC
collapses below
level (typically
Figure 36. Current Control
to
Standby Management
(Skipping, GTS)
Soft−Start
oscillator
Pin 5 (Brown−Out)
http://onsemi.com
Aux
CC
NCP1239
17
delivered on Pin 12 and the auxiliary winding grows up the
V
SMPS is starting up), the feedback pin is at its maximum
voltage. A resistor divider outputs the third of the feedback
voltage that forms the current setpoint. This setpoint is
clamped and the limitation level slowly increases until it
reaches 0.9V during the soft start time. In nominal operation,
the setpoint clamp keeps equal to 0.9 V (refer to Figure 36).
the 0.9 V setpoint clamp (during the startup period but also
anytime an overload occurs), an internal error flag is
asserted, testifying that the system is pushed to the
maximum power. At that moment, a 100 ms time period
(typically, with C
soft −start) starts while a logic block observes this error flag.
If the error flag keeps asserted all along the 100ms period,
then the controller assumes that the power supply really
undergoes a fault condition and immediately stops all pulses
to enter a safe burst operation. The 100 ms timer enables to
distinguish a startup phase (shorter than 100 ms) from an
overload condition. If the error flag is released before the
100 ms period has elapsed, the controller concludes that no
error is present and resets the timer to use it for other
purposes (e.g. frequency dithering).
CC
As soon as V
As soon as the feedback voltage is high enough to activate
pin. Because the output voltage is below the target (the
Over Power
Limit
Feedback
Current Sense
10
8
9
pin6
CC
=390 nF that also corresponds to 7.5 ms
reaches 16.4 V, driving pulses are
Rcomp
Rramp
Vin
Rsense