ncp1239f ON Semiconductor, ncp1239f Datasheet - Page 33
![no-image](/images/manufacturer_photos/0/4/495/on_semiconductor_sml.jpg)
ncp1239f
Manufacturer Part Number
ncp1239f
Description
Lowstandby High Performance Pwm Controller
Manufacturer
ON Semiconductor
Datasheet
1.NCP1239F.pdf
(38 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Skipping Cycle Mode
the output power demand drops below a given level. This is
accomplished by monitoring the FB pin. In normal
operation, Pin 8 imposes a current setpoint accordingly to
the load value. If the load demand decreases, the internal
loop asks for less peak current. When this setpoint reaches
a fixed determined level, the IC prevents the current from
decreasing further down and starts to blank the output
pulses: the IC enters the so−called skip−cycle mode, also
named controlled burst operation. The default skip−cycle
current is internally frozen to 30% of the maximum peak
current which is 0.5 V/Rsense The power transfer now
depends upon the width of the pulse bunches (Figure 54).
default), the circuit skips the switching cycle. When the IC
enters the skip−cycle mode, the peak current cannot go
The NCP1239 automatically skips switching cycles when
When FB is below the skip−cycle threshold (0.43 V by
FB Pin Voltage
Output pulses at various power levels (X = 5ms/div) P1 < P2 < P3
Normal current mode operation
Skip−cycle operation
Ip
MIN
= 150 mV/Rsense
http://onsemi.com
Figure 54.
NCP1239
Figure 55.
33
Suppose we have the following component values:
The theoretical power transfer is therefore:
10 ms over a recurrent period of 100 ms, then the total power
transfer is:
place, a look at the operation mode versus the FB level
immediately gives the necessary insight:
below (0.43 V/3)/Rsense or 140 mV/Rsense. Figure 55
shows different values of pulse widths when the SMPS starts
to skip−cycles at different power levels:
Lp, primary inductance = 350 mH
fsw , switching frequency = 65 kHz
Ip skip = 600 mA (or 140 mV/Rsense)
1/2 * Lp * Ip
If this IC enters skip−cycle mode with a bunch length of
4 W * 10 ms/100 ms = 400 mW
To better understand how this skip−cycle mode takes
2
* fsw = 4 W
0.43 V
4.3 V, FB Pin open
2.7 V upper dynamic range
Power P1
Power P2
Power P3