lm26003mhx National Semiconductor Corporation, lm26003mhx Datasheet - Page 11

• Manufacturer Part Number: lm26003mhx
• Description: 3a Switching Regulator With High Efficiency Sleep Mode
• Manufacturer: National Semiconductor Corporation

UVLO is sensed at both VIN and VDD, and is activated when
either voltage falls below 2.96V (typical). Although VDD is
typically less than 200 mV below VIN, it will not discharge
through VIN. Therefore when the VIN voltage drops rapidly,
VDD may remain high, especially in sleep mode. For fast line
voltage transients, using a larger capacitor at the VDD pin can
help to hold off a UVLO shutdown by extending the VDD dis-
charge time. By holding up VDD, a larger cap can also reduce
the R
ternately, under heavy loading the VDD voltage can fall sev-
eral hundred mV below VIN. In this case, UVLO may be
triggered by VDD even though the VIN voltage is above the
UVLO threshold.
When UVLO is activated the LM26003 enters a standby state
in which VDD remains charged. As input voltage and VDD
voltage rise above 3.99V (typical) the device will restart from
soft-start mode.
DS(ON)
FIGURE 6. Off-Pulse Skipping Waveforms
Vin = 3.5V, Vnom = 3.3V, fnom = 305 kHz
(and dropout voltage) in low VIN conditions. Al-
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FIGURE 7. Example Circuit
3A, 300 kHz
11
PGOOD
A power good pin, PGOOD, is available to monitor the output
voltage status. The pin is internally connected to an open
drain MOSFET, which remains open while the output voltage
is within operating range. PGOOD goes low (low impedance
to ground) when the output falls below 89% of nominal or EN
is pulled low. When the output voltage returns to within 95%
of nominal, as measured at the FB pin, PGOOD returns to a
high state. For improved noise immunity, there is a 5 µs delay
between the PGOOD threshold and the PGOOD pin going
low.
Design Information
EXAMPLE CIRCUIT
Figure 7 shows a complete typical application schematic. The
components have been selected based on the design criteria
given in the following sections.
SETTING OUTPUT VOLTAGE
The output voltage is set by the ratio of a voltage divider at
the FB pin as shown in the typical application. The resistor
values can be determined by the following equation:
Where Vfb = 1.236V typically.
A maximum value of 150 kΩ is recommended for the sum of
R1 and R2.
As input voltage decreases towards the nominal output volt-
age, the LM26003 can skip up to seven off-pulses as de-
scribed in the Low Vin Operation section. In low output voltage
applications, if the on-time reaches Ton
skip on-pulses to maintain regulation. There is no limit to the
number of pulses that are skipped. In this mode of operation,
however, output ripple voltage may increase slightly.
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MIN
, the device will
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