x3101 Intersil Corporation, x3101 Datasheet - Page 13

• Manufacturer Part Number: x3101
• Description: 3 Or 4 Cell Li-ion Battery Protection And Monitor Ic
• Manufacturer: Intersil Corporation

Bit 1 of the status register simply indicates whether or
not the X3100 or X3101 is in over-discharge protec-
tion mode.
Bit 2 of the status register (CCES+OVDS) indicates
the status of two conditions of the X3100 or X3101.
Cell Charge Enable Status (CCES) is an internally
generated signal which indicates the status of any cell
voltage (V
Voltage (V
(OVDS) is an internally generated signal which indi-
cates whether or not the X3100 or X3101 is in over-
charge protection mode.
Table 18. Status Register Functionality.
Notes:
X3100/X3101 INTERNAL PROTECTION FUNCTIONS
The X3100 and the X3101 provide periodic monitoring
(see section “Periodic Protection Monitoring” on page
13) for over-charge and over-discharge states and
continuous monitoring for an over-current state. It has
automatic shutdown when a protection mode is
encountered, as well as automatic return after the
device is released from a protection mode. When sam-
pling voltages through the analog port (Monitor Mode),
over-charge and over-discharge protection monitoring
is also performed on a continuous basis.
Voltage thresholds for each of these protection modes
(V
selected via software and stored in an internal non-vol-
atile register. This feature allows the user to avoid the
restrictions of mask programmed voltage thresholds, and
is especially useful during prototype/evaluation design
stages or when cells with slightly different characteris-
tics are used in an existing design.
Bit(s)
3 - 7
OV
0
1
2
, V
†
This bit is set in the configuration register.
UV
VRGS+OCDS Voltage regulator
CCES+OVDS
CELL
, and V
CE
Name
UVDS
). Over-charge Voltage Detection Status
) with respect to the Cell Charge Enable
-
OC
respectively) can be individually
detection status
detection status
detection status
Over-discharge
enable status
Description
13
Over-current
Over-charge
Cell charge
status
+
+
SWCEN =0
SWCEN =1
Case
-
-
-
X3100, X3101
†
†
Status
1
0
1
0
1
0
1
0
0
When the cell charge enable function is switched ON
(configuration bit SWCEN=0), the signals CCES and
OVDS are logically OR’ed (CCES+OVDS) and written
to bit 2 of the status register. If the cell charge enable
function
SWCEN=1), then bit 2 of the status register effectively
only represents information about the over-charge sta-
tus (OVDS) of the X3100 or X3101 (See Table 18,
Table 17 and Figure ).
Delay times for the detection of, and release from protec-
tion modes (T
can be individually varied by setting the values of
external capacitors connected to pins OVT, UVT, OCT.
Periodic Protection Monitoring
In normal operation, the analog select pins are set
such that AS2 = L, AS1 = L, AS0 = L. In this mode the
X3100 and X3101 conserve power by sampling the
cells for over or over-discharge conditions.
In this state over-charge and over-discharge protec-
tion circuitry are usually off, but are periodically
switched on by the internal Protection Sample Rate
Timer (PSRT). The over-charge and over-discharge
protection circuitry is on for approximately 2ms in each
125ms period. Over-current monitoring is continuous.
In monitor mode (see page 21) over-charge and over-
discharge monitoring is also continuous.
V
X3100/X3101 in over-current protection mode.
V
X3100/X3101 NOT in over-current protection mode.
X3100/X3101 in over-discharge protection mode
X3100/X3101 NOT in over-discharge protection mode
V
X3100/X3101 in over-charge protection mode
V
X3100/X3101 NOT in over-charge protection mode
X3100/X3101 in over-charge protection mode
X3100/X3101 NOT in over-charge protection mode
Not used (always return zero)
RGO
RGO
CELL
CELL
not yet tuned (V
tuned (V
< V
> V
is
CE
CE
OV
OR
AND
switched
RGO
, T
UV
Interpretation
= 5V ± 0.5%) AND
/T
UVR
RGO
, and T
= 5V ± 10%) OR
OFF
OC
(configuration
/T
OCR
respectively)
January 3, 2008
FN8110.1
bit