stm8af6148 STMicroelectronics, stm8af6148 Datasheet - Page 14

• Manufacturer Part Number: stm8af6148
• Description: Automotive 8-bit Mcu, With Up To 32 Kbytes Flash, Eeprom, 10-bit Adc, Timers, Lin, Spi, I 2c, 3 V To 5.5 V
• Manufacturer: STMicroelectronics

Product overview
5.4.3
5.4.4
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Read-out protection (ROP)
STM8A devices provide a read-out protection of the code and data memory by
programming the lock byte at address 4800h with the value AAh.
Read-out protection prevents reading and writing the program and data memory via the
debug module and SWIM interface. This protection is active in all device operation modes.
Any attempt to remove the protection by overwriting the lock byte triggers a global erase of
the program and data memory.
The ROP circuit may provide a temporary access for debugging or failure analysis. This is a
specific product option and must be specified while ordering STM8A products.
Temporary read access is protected by a user defined, 8-byte keyword that is different from
00h or FFh. The keys are stored in the option byte area.
Temporary read-out can be permanently disabled by means of the option byte TMU_DIS.
For enabling temporary read access the eight access keys have to be written in the TMU
registers. A wrong code does not change the protection status. More than eight
unsuccessful access trials trigger an erase of the program and data memory.
Entering the right key sequence enables a temporary read access to the code and data
memory after a delay of several milliseconds.
The procedure for temporary read access is as follows:
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The read access is temporary. A device reset restores the initial protection.
Speed
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Activate SWIM mode under device reset - the CPU is stalled, code and data memory
are not visible by the debug module.
Enable the internal 128 KHz LSI oscillator
Write the 8eight key bytes into the TMU registers
Set the bit(0) of the TMU status register to 1. A dedicated state machine on an isolated
bus, compares the TMU register content with the key stored in the TMU option bytes.
During this periode read and write operations have no effect. A reset re-activates the
initial protection status. The comparison can be monitored by means of the
register.
In case of a successful key comparison, the SWIM interface enables read access to the
code and data memory and program execution. A comparison error does not change
the protection status but increments the counter MAXATT. If the counter content
exceedes eight unsuccessful trials, a global erase of the data and code memory is
triggered.
Operation at up to 16 MHz CPU clock frequency without wait states.
Programming time modes (same for word or block)
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Fast programming: Without erase
Standard programming: Erase and program
STM8AF61xx STM8AH61xx
TU_CTL_ST