el7156 Intersil Corporation, el7156 Datasheet - Page 8

• Manufacturer Part Number: el7156
• Description: High Performance Pin Driver
• Manufacturer: Intersil Corporation

Applications Information
Product Description
The EL7156 is a high performance 40MHz pin driver. It
contains two analog switches connecting VH and VL to OUT.
Depending on the value of the IN pin, one of the two
switches will be closed and the other switch open. An output
enable (OE) is also supplied which opens both switches
simultaneously.
Due to the topology of the EL7156, both the VH and VL pins
can be connected to any voltage between the VS+ and VS-
pins, but VH must be greater than VL in order to prevent
turning on the body diode at the output stage.
The EL7156 is available in both the 8 Ld SOIC and the 8 Ld
PDIP packages. The relevant package should be chosen
depending on the calculated power dissipation.
Three-state Operation
When the OE pin is low, the output is three-state (floating).
The output voltage is the parasitic capacitance’s voltage. It
can be any voltage between VH and VL, depending on the
previous state. At three-state, the output voltage can be
pushed to any voltage between VH and VL. The output
voltage can’t be pushed higher than VH or lower than VL
since the body diode at the output stage will turn on.
Supply Voltage Range and Input Compatibility
The EL7156 is designed for operation on supplies from 5V to
15V (4.5V to 16.5V maximum). “Operating Voltage Range”
on page 6 shows the specifications for the relationship
between the VS+, VS-, VH, VL, and GND pins.
All input pins are compatible with both 3V and 5V CMOS
signals. With a positive supply (V
also compatible with TTL inputs.
Power Supply Bypassing
When using the EL7156, it is very important to use adequate
power supply bypassing. The high switching currents
developed by the EL7156 necessitate the use of a bypass
capacitor between the supplies (VS+ and VS-) and GND
pins. It is recommended that a 2.2µF tantalum capacitor be
used in parallel with a 0.1µF low-inductance ceramic MLC
capacitor. These should be placed as close to the supply
pins as possible. It is also recommended that the VH and VL
pins have some level of bypassing, especially if the EL7156
is driving highly capacitive loads.
Power Dissipation Calculation
When switching at high speeds, or driving heavy loads, the
EL7156 drive capability is limited by the rise in die
temperature brought about by internal power dissipation. For
reliable operation, die temperature must be kept below
T
dissipation for a given application prior to selecting the
package type.
JMAX
(+125°C). It is necessary to calculate the power
8
S
+) of 5V, the EL7156 is
EL7156
Power dissipation may be calculated:
where:
Having obtained the application’s power dissipation, a
maximum package thermal coefficient may be determined,
to maintain the internal die temperature below T
where:
θ
PDIP8 package when using a standard JEDEC JESD51-3
single-layer test board. If T
when calculated using Equation 2, then one of the following
actions must be taken:
PD
θ
JA
JA
V
GND)
V
C
C
I
f is frequency
T
T
PD is the power dissipation calculated above
θ
Reduce θ
into the PCB (as compared to the standard JEDEC
JESD51-3).
Use the PDIP8 instead of the SOIC8 package.
De-rate the application either by reducing the switching
frequency, the capacitive load, or the maximum operating
(ambient) temperature (T
S
JA
S
OUT
JMAX
MAX
VS
INT
is 160°C/W for the SOIC8 package and 100°C/W for the
=
is the quiescent supply current (3mA max)
=
V
is the total power supply to the EL7156 (from V
thermal resistance on junction to ambient
(
S
V
is the integral capacitance due to V
T
---------------------------------------- -
is the integral load capacitance due to V
+ = V
is the swing on the output (V
JMAX
is the maximum operating temperature
S
is the maximum junction temperature (+125°C)
10
15
×
5
JA
I
PD
S
TABLE 1. INTEGRAL CAPACITANCE
H
–
)
(V)
the system by designing more heat-sinking
+
T
(
MAX
C
VS
×
V
S
2
JMAX
MAX
×
C
f )
VS
).
+
80
85
90
is greater than +125°C
(pF)
[
(
C
INT
H
to V
+
C
S
L
L
+
)
)
×
V
H
C
JMAX
OUT
INT
120
145
180
May 2, 2007
(pF)
S
2
:
(EQ. 1)
(EQ. 2)
FN7280.3
+ to
×
f
]