dm9332 Davicom Semiconductor, Inc., dm9332 Datasheet - Page 43

• Manufacturer Part Number: dm9332
• Description: 10/100mbps Ethernet Fiber/twisted Pair Single Chip Media Converter
• Manufacturer: Davicom Semiconductor, Inc.

9. Functional Description
9.1 Serial Management Interface
Host SMI - Read Frame Structure
Host SMI - Write Frame Structure
DM9332 supports two type of serial management
interface (SMI), Host SMI and MII SMI. The
application of SMI illustrated as below.
1. The Host SMI consists of two pins, one is SMI_CK
and another is SMI_DIO. User can access DM9332’s
EEPROM, PHY registers, MIB counters and
Configuration registers through Host SMI. The format
is following. The <Device Address> field of the frame
means SMI device address that is configured by strap
Preliminary datasheet
DM9332-15-DS-P01
August 26, 2009
SMI_DIO Read
SMI_DIO Write
(SMI device address = 0~3)
SMI_CK
SMI_CK
DM9332
Idle
Idle
Preamble
32 "1"s
Preamble
32 "1"s
SMI_DIO
SMI_CK
MDIO
MDC
0
0
SFD
SFD
1
1
MII SMI
Host SMI
Only one host is allowed to acccess the SMI_CK, SMI_DIO
1
Op Code
0
Op Code
External PHY can be accessed via the MDC, MDIO
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
0
1
Write
MDC
MDIO
MDC
MDIO
Device Address
Device Address
A1
A1
A0
A0
Host / MAC
Port2 PHY
(PHY Address =
R7
R7
Register Address
Write
2)
R6
R6
Register Address
pin (TXD2_0 & TXD2_1). The <Register Address>
field of the frame is mapped to address of control and
status register set of DM9332. The read/writ data is
valid on low byte (D7~D0) of <Data> field, the high
byte (D15~D8) of data is reserved.
2. DM9332 supports MII SMI auto-polling for
configuring speed, duplex mode, and 802.3x flow
control capability of the external PHY (Port2) via the
MDC, MDIO. More detail description and frame
format can refer to section 9.3.2.
R5
R5
R0
R0
Z
Turn Around
Turn Around
1
0
0
D15
D15
D14
D14
Read
Data
Data
//
D1
D1
DM9332
D0
D0
Idle
Idle
//
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