dm9332 Davicom Semiconductor, Inc., dm9332 Datasheet - Page 52

• Manufacturer Part Number: dm9332
• Description: 10/100mbps Ethernet Fiber/twisted Pair Single Chip Media Converter
• Manufacturer: Davicom Semiconductor, Inc.

The 100Base-TX receiver contains several function
blocks that convert the scrambled 125Mb/s serial
data to synchronous 4-bit nibble data.
The receive section contains the following functional
blocks:
- Signal Detect
- Digital Adaptive Equalization
- MLT-3 to Binary Decoder
- Clock Recovery Module
- NRZI to NRZ Decoder
- Serial to Parallel
- Descrambler
- Code Group Alignment
- 4B5B Decoder
The signal detects function meets the specifications
mandated by the ANSI XT12 TP-PMD 100Base-TX
standards for both voltage thresholds and timing
parameters.
When transmitting data over copper twisted pair
cable at high speed, attenuation based on frequency
becomes a concern. In high speed twisted pair
signaling, the frequency content of the transmitted
signal can vary greatly during normal operation based
on the randomness of the scrambled data stream.
This variation in signal attenuation, caused by
frequency variations, must be compensated for to
ensure the integrity of the received data. In order to
ensure quality transmission when employing MLT-3
encoding, the compensation must be able to adapt to
various cable lengths and cable types depending on
the installed environment. The selection of long cable
lengths
significant compensation, which will be over-killed in
a situation that includes shorter, less attenuating
cable lengths. Conversely, the selection of short or
intermediate
compensation will cause serious under-compensation
for longer length cables. Therefore, the compensation
or equalization must be adaptive to ensure proper
conditioning of the received signal independent of the
cable length.
52
9.4.2 100Base-TX Receiver
9.4.2.1 Signal Detect
9.4.2.2 Adaptive Equalization
for
a
cable
given
lengths
implementation
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
requiring
requires
less
The DM9332 decodes the MLT-3 information from
the Digital Adaptive Equalizer into NRZI data.
The Clock Recovery Module accepts NRZI data from
the MLT-3 to NRZI decoder. The Clock Recovery
Module locks onto the data stream and extracts the
125 MHz reference clock. The extracted and
synchronized clock and data are presented to the
NRZI to NRZ decoder.
The transmit data stream is required to be NRZI
encoded for compatibility with the TP-PMD standard
for
unshielded twisted pair cable. This conversion
process must be reversed on the receive end. The
NRZI to NRZ decoder receives the NRZI data stream
from the Clock Recovery Module and converts it to a
NRZ data stream to be presented to the Serial to
Parallel conversion block.
The Serial to Parallel Converter receives a serial data
stream from the NRZI to NRZ converter. It converts
the data stream to parallel data to be presented to the
descrambler.
Because of the scrambling process requires to
control the radiated emissions of transmit data
streams, the receiver must descramble the receive
data streams. The descrambler receives scrambled
parallel data streams from the Serial to Parallel
converter, and it descrambles the data streams, and
presents the data streams to the Code Group
alignment block.
100Base-TX
9.4.2.3 MLT-3 to NRZI Decoder
9.4.2.4 Clock Recovery Module
9.4.2.5 NRZI to NRZ
9.4.2.6 Serial to Parallel
9.4.2.7 Descrambler
transmission
over
DM9332
Preliminary datasheet
DM9332-15-DS-P01
Category-5
August 26, 2009