lm5021na-2 National Semiconductor Corporation, lm5021na-2 Datasheet - Page 8

• Manufacturer Part Number: lm5021na-2
• Description: Ac-dc Current Mode Pwm Controller
• Manufacturer: National Semiconductor Corporation

www.national.com
Detailed Operating Description
RELATIONSHIP BETWEEN INPUT CAPACITOR C
V
The internal VCC linear regulator is enabled when VIN
reaches 20V. The drop in VIN due to charge transfer from
C
from the following equations where VIN’ is the voltage on
C
Assuming C
drop in VIN will be 0.85V, or the VIN value drops to 19.15V.
The value of the VCC capacitor can be small (less than 1uF)
as it supplies only transient gate drive current of a short
duration. The C
gate drive current and the quiescent current of LM5021until
the transformer bias winding delivers sufficient voltage to
VIN to sustain the VCC voltage.
The C
ing VCC load current after it’s output voltage reaches the
VCC UVLO threshold. For example, if the LM5021 is driving
an external MOSFET with total gate charge (Qg) of 25nC,
the average gate drive current is Qg x Fsw, where Fsw is the
switching frequency. Assuming a switching frequency of
150KHz, the average gate drive current is 3.75mA. Since the
IC consumes approximately 2.5mA operating current in ad-
dition to the gate current, the total current drawn from C
capacitor is the operating current plus the gate charge cur-
rent, or 6.25mA. The C
for a brief time until the transformer bias winding takes over.
The C
sequence or the cycle will be restarted. The maximum allow-
able start-up time can be calculated using the value of C
the change in voltage allow at VIN (19.15V – 8.5V) and the
VCC regulator current (6.25mA). Tmax, the maximum time
allowed to energize the bias winding is:
If the calculated value of Tmax is too small, the value of Cin
should be increased further to allow more time before the
transformer bias winding takes over and delivers the oper-
ating current to the VCC regulator. Increasing C
crease the time from the application of the rectified ac (HV in
the Figure 2) to the time when VIN reaches the 20V start
threshold. The initial charging time of C
(Continued)
CC
VIN
VIN
CAPACITOR C
to C
immediately after the VCC regulator charges C
VIN
VIN
VCC
voltage must not fall below 8.5V during the start-up
capacitor value can be calculated from the operat-
VIN
after the regulator is enabled can be calculated
(20V – V
∆VIN x C
value as 10 µF, and C
VIN
VCC
capacitor must be sized to supply the
VIN
IN’
VIN
) C
capacitor must supply this current
= ∆VCC x C
VIN
= 8.5V C
VCC
VIN
VCC
VCC
is:
of 1µF, then the
VIN
IN
VCC
will in-
&
VIN
.
VIN
,
8
PWM COMPARATOR/SLOPE COMPENSATION
The PWM comparator compares the current sense signal
with the loop error voltage from the COMP pin. The COMP
pin voltage is reduced by 1.25V then attenuated by a 3:1
resistor divider. The PWM comparator input offset voltage is
designed such that less than 1.25V at the COMP pin will
result in a zero duty cycle at the controller output.
For duty cycles greater than 50 percent, current mode con-
trol circuits are subject to sub-harmonic oscillation. By add-
ing an additional fixed slope voltage ramp signal (slope
compensation) to the current sense signal, this oscillation
can be avoided. The LM5021-1 integrates this slope com-
pensation by summing a ramp signal generated by the os-
cillator with the current sense signal. The slope compensa-
tion is generated by a current ramp driven through an
internal 1.8 kΩ resistor connected to the CS pin. Additional
slope compensation may be added by increasing the resis-
tance between the current sense filter capacitor and the CS
pin, thereby increasing the voltage ramp created by the
oscillator current ramp. Since the LM5021-2 is not capable of
duty cycles greater than 50%, there is no slope compensa-
tion feature in this device.
CURRENT LIMIT/CURRENT SENSE
The LM5021 provides a cycle-by-cycle over current protec-
tion feature. Current limit is triggered by an internal current
sense comparator threshold which is set at 500mV. If the CS
pin voltage plus the slope compensation voltage exceeds
500mV, the OUT pin output pulse will be immediately termi-
nated.
An RC filter, located near the LM5021, is recommended for
the CS pin to attenuate the noise coupled from the power
FET’s gate to source. The CS pin capacitance is discharged
at the end of each PWM clock cycle by an internal switch.
The discharge switch remains on for an additional 90ns
leading edge blanking interval to attenuate the current sense
transient that occurs when the external power FET is turned
on. In addition to providing leading edge blanking, this circuit
also improves dynamic performance by discharging the cur-
rent sense filter capacitor at the conclusion of every cycle.
The LM5021 CS comparator is very fast, and may respond
to short duration noise pulses. Layout considerations are
critical for the current sense filter and sense resistor. The
capacitor associated with the CS filter must be placed very
close to the device and connected directly to the pins of the
IC (CS and GND). If a current sense transformer is used,
both leads of the transformer secondary should be routed to
the sense resistor, which should also be located close to the
IC. If a current sense resistor located in the power FET’s
source is used for current sense, a low inductance resistor is
required. In this case, all of the noise sensitive low current
grounds should be connected in common near the IC and
then a single connection should be made to the power
ground (sense resistor ground point).
OSCILLATOR, SHUTDOWN and SYNC CAPABILITY
A single external resistor connected between RT and GND
pins sets the LM5021 oscillator frequency. The LM5021-2
device, with 50% maximum duty cycle, includes an internal
flip-flop that divides the oscillator frequency by two. This
method produces a precise 50% maximum duty cycle limit.
Because of this frequency divider, the oscillator frequency of
the LM5021-2 is actually twice the frequency of the gate
drive output (OUT). For the LM5021-1 device, the oscillator