lm5035mhx National Semiconductor Corporation, lm5035mhx Datasheet - Page 3

• Manufacturer Part Number: lm5035mhx
• Description: Pwm Controller With Integrated Half-bridge And Syncfet Drivers
• Manufacturer: National Semiconductor Corporation

TSSOP
Ordering Information
Pin Descriptions
PIN
1
2
3
4
5
6
7
8
9
Order Number
LM5035MH
LM5035MHX
LM5035SQ
LM5035SQX
LLP
PIN
23
24
2
3
4
5
6
7
8
COMP
RAMP
AGND
Name
UVLO
OVP
DLY
RT
CS
SS
Modulator ramp signal
Line Under-Voltage Lockout
Line Over-Voltage Protection
Input to the Pulse Width
Modulator
Oscillator Frequency Control and
Sync Clock Input.
Analog Ground
Current Sense input for current
limit
Soft-start Input
Timing programming pin for the
LO and HO to SR1 and SR2
outputs.
Package Type
TSSOP-20EP
TSSOP-20EP
LLP-24
LLP-24
Description
NSC Package Drawing
MXA20A
MXA20A
SQA24B
SQA24B
3
An external RC circuit from VIN sets the ramp slope. This pin
is discharged at the conclusion of every cycle by an internal
FET. Discharge is initiated by either the internal clock or the
Volt • Second clamp comparator.
An external voltage divider from the power source sets the
shutdown and standby comparator levels. When UVLO
reaches the 0.4V threshold the VCC and REF regulators are
enabled. When UVLO reaches the 1.25V threshold, the SS pin
is released and the device enters the active mode. Hysteresis
is set by an internal current sink that pulls 23µA from the
external resistor divider.
An external voltage divider from the power source sets the
shutdown levels. The threshold is 1.25V. Hysteresis is set by
an internal current source that sources 23µA into the external
resistor divider.
An external opto-coupler connected to the COMP pin sources
current into an internal NPN current mirror. The PWM duty
cycle is maximum with zero input current, while 1mA reduces
the duty cycle to zero. The current mirror improves the
frequency response by reducing the AC voltage across the
opto-coupler detector.
Normally biased at 2V. An external resistor connected between
RT and AGND sets the internal oscillator frequency. The
internal oscillator can be synchronized to an external clock with
a frequency higher than the free running frequency set by the
RT resistor.
Connect directly to Power Ground.
If CS exceeds 0.25V the output pulse will be terminated,
entering cycle-by-cycle current limit. An internal switch holds
CS low for 50ns after HO or LO switches high to blank leading
edge transients.
An internal 55 µA current source charges an external capacitor
to set the soft-start rate. During a current limit restart
sequence, the internal current source is reduced to 1.2µA to
increase the delay before retry.
An external resistor to ground sets the timing for the
non-overlap time of HO to SR1 and LO to SR2.
Application Information
Supplied As
73 Units per Rail
2500 Units on Tape and Reel
1000 Units on Tape and Reel
4500 Units on Tape and Reel
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