lm5039mhx National Semiconductor Corporation, lm5039mhx Datasheet - Page 3

• Manufacturer Part Number: lm5039mhx
• Description: Half-bridge Pwm Controller With Average Current Limit
• Manufacturer: National Semiconductor Corporation

Order Number
LM5039MH
LM5039MHX
TSSOP
Ordering Information
Pin Descriptions
Pin
1
2
3
4
5
6
7
8
LLP Pin
23
24
2
3
4
5
6
7
COMP
RAMP
AGND
Name
UVLO
ACL
RT
CS
SS
Package Type
TSSOP-20EP
TSSOP-20EP
Modulator ramp signal
Line Under-Voltage Lockout
Average Current Limit
Input to the Pulse Width Modulator An external opto-coupler connected to the COMP pin sources
Oscillator Frequency Control and
Sync Clock Input.
Analog Ground
Current Sense input for current
limit
Soft-start Input
Description
3
NSC Package Drawing
MXA20A
MXA20A
An external RC circuit from VIN sets the ramp slope. This pin is
discharged at the conclusion of every cycle by an internal FET.
Discharge is initiated by either the internal clock or the Volt •
Second clamp comparator.
An external voltage divider from the power source sets the
shutdown and standby comparator levels. When UVLO reaches
the 0.4V threshold the VCC and REF regulators are enabled.
When UVLO reaches the 1.25V threshold, the SS pin is released
and the device enters the active mode. Hysteresis is set by an
internal current source that sources 23 µA into the external
resistor divider.
A capacitor connected between the ACL pin and GND operates
as an integrator in the average current limit circuitry. The ACL
capacitor is charged during current limit condition. As the ACL pin
voltage rises, it terminates the cycle through the PWM
comparator by pulling down the input of the comparator that is
normally controlled through the COMP pin. This maintains equal
pulse-widths in both the phases of the half-bridge and thereby
maintains balance of the half-bridge capacitor voltages.
current into an internal NPN current mirror. The PWM duty cycle
is maximum with zero input current, while 1mA reduces the duty
cycle to zero. The current mirror improves the frequency
response by reducing the AC voltage across the opto-coupler
detector.
Normally regulated at 2V. An external resistor connected
between RT and AGND sets the internal oscillator frequency. The
internal oscillator can be synchronized to an external clock with
a frequency higher than the free running frequency set by the RT
resistor.
Connect directly to Power Ground.
The CS pin is driven by a signal representative of the primary
current. A higher threshold (600mV) comparator is used to
implement a fast peak cycle-by-cycle current limit to provide
instant protection to the power converter. A lower threshold
(500mV) comparator is used to implement a slower average
current limit that maintains the balance of the half-bridge
capacitor divider voltage. A 50ns blanking time at the CS pin
avoids false tripping the current limit comparators due to leading
edge transients.
An internal 110µA current source charges an external capacitor
to set the soft-start rate. During a current limit restart sequence,
the internal current source is reduced to 1.2µA to increase the
delay before retry.
Application Information
Supplied As
73 Units per Rail
2500 Units on Tape and Reel
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