lm5072mhx-80 National Semiconductor Corporation, lm5072mhx-80 Datasheet - Page 19

• Manufacturer Part Number: lm5072mhx-80
• Description: Integrated 100v Power Over Ethernet Pd Interface And Pwm Controller With Aux Support
• Manufacturer: National Semiconductor Corporation

For isolated applications, the error amplifier function is locat-
ed on the isolated secondary side. The LM5072’s error am-
plifier can be disabled by connecting the FB pin to the ARTN
pin. As shown in Figure 14, an opto-coupler is normally used
to send the feedback signal across the isolation boundary to
the COMP pin. The internal pull-up resistor on the COMP pin
now serves as the pull-up bias for the opto-coupler transistor.
Current Sense and Limit
The LM5072 CS pin senses the transformer primary current
signal for current mode control and current limiting of the sup-
ply. As shown in Figure 15, the current sense function can be
fulfilled by a simple sense resistor R
the RTN and the source of the primary MOSFET switch.
The R
filter should be used to reject the switching noise on the
sensed signal. A simple RC filter using 100Ω and 1 nF is typ-
ically sufficient. The filter capacitor must be located close to
the CS and ARTN pins. In order to prevent noise propagation
and to improve the noise immunity of the current sense, it is
very important to minimize the return path of the current sense
signal. This is accomplished with direct connection to the
ARTN pin and a single point connection to the RTN pin on the
PC Board layout.
FIGURE 14. The Internal Error Amplifier – Bypassed in
FIGURE 13. Internal Error Amplifier – Used for Non-
SENSE
resistor should be non-inductive, and a low pass
isolated Output Applications
Isolated Output Applications
SENSE
inserted between
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The current sense signal is also used for cycle-by-cycle over-
current protection. When the CS pin signal exceeds 0.5V, the
PWM pulse of that cycle will be immediately terminated. The
desired cycle-by-cycle over-current protection level is
achieved by selecting the proper value of current sense re-
sistor that produces 0.5V at the CS pin. For the LM5072-80,
the slope compensation reduces the current limit threshold by
about 20% maximum at the 80% maximum duty cycle.
The typical current sense waveform as shown in Figure 16
has a spike at the leading edge. This spike is mainly caused
by the large gate drive current that flows through the current
sense resistor at turn-on (up to 0.8A). The reverse recovery
of the rectifier diode on the secondary side and the cross
conduction of the primary MOSFET and sync MOSFET (if
used) may also contribute to this leading edge spike. With a
relatively small external RC filter, this spike can still cause a
false over-current condition that terminates the PWM output
pulse. To avoid this problem, an internal blanking circuit is
provided within the LM5072 as shown in Figure 15. An internal
MOSFET is turned on to short the CS pin to ARTN at the end
of each cycle. This MOSFET switch remains on for an addi-
tional 65ns after the beginning of the next PWM cycle, thus
blanking out the leading edge spike on the current sense sig-
nal.
Soft-Start
The LM5072 incorporates a soft-start feature which forces the
PWM duty cycle to grow progressively during startup such
that the output voltage increases gradually to the steady state
level. The soft-start process reduces or prevents both the
surge of inrush current and the associated overshoot of the
output voltage during startup. The LM5072 achieves soft-start
using an internal 10 µA current source to charge an external
capacitor connected to the SS pin. The capacitor voltage lim-
its the voltage at the COMP pin which directly controls the
PWM duty cycle. The rate of the soft-start ramp can be ad-
justed by varying the value of the external capacitor. Note that
the slope of the supply’s output voltage is influenced by the
load condition and the total output capacitance of the supply,
as well as the soft-start programming. The supply should be
FIGURE 16. Typical Current Sense Waveform Having a
FIGURE 15. Current Sense Schemes
Leading Edge Spike
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