x9520v20iz-bt1 Intersil Corporation, x9520v20iz-bt1 Datasheet - Page 3

• Manufacturer Part Number: x9520v20iz-bt1
• Description: Fiber Channel/gigabit Ethernet Laser Diode Control For Fiber Optic Modules Triple Dcp, Por, 2kbit Eeprom Memory, Dual Voltage Monitors
• Manufacturer: Intersil Corporation

Pinout
Pin Descriptions
TSSOP
10
12
13
14
15
16
17
18
11
1
2
3
4
5
6
7
8
9
NAME
V3RO
V2RO
SDA
R
R
R
SCL
R
R
R
R
R
R
MR
WP
Vss
V3
V2
W0
H2
w2
w1
H1
H0
L2
L1
L0
Connection to end of resistor array for (the 256 Tap) DCP 2.
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 2.
Connection to other end of resistor array for (the 256 Tap) DCP 2.
V3 Voltage Monitor Input. V3 is the input to a non-inverting voltage comparator circuit. When the V3 input is higher than the
V
V3 RESET Output. This open drain output makes a transition to a HIGH level when V3 is greater than V
when V3 is less than VTRIP3. There is no delay circuitry on this pin. The V3RO pin requires the use of an external “pull-up”
resistor.
Manual Reset. MR is a TTL level compatible input. Pulling the MR pin active (HIGH) initiates a reset cycle to the V1RO pin
(V1/VCC RESET Output pin). V1RO will remain HIGH for time t
reset time can be selected using bits POR1 and POR0 in the CONSTAT Register. The MR pin requires the use of an external
“pull-down” resistor.
Write Protect Control Pin. WP pin is a TTL level compatible input. When held HIGH, Write Protection is enabled. In the enabled
state, this pin prevents all nonvolatile “write” operations. Also, when the Write Protection is enabled, and the device Block Lock
feature is active (i.e. the Block Lock bits are NOT [0,0]), then no “write” (volatile or nonvolatile) operations can be performed
in the device (including the wiper position of any of the integrated Digitally Controlled Potentiometers (DCPs). The WP pin
uses an internal “pull-down” resistor, thus if left floating the write protection feature is disabled.
Serial Clock. This is a TTL level compatible input pin used to control the serial bus timing for data input and output.
Serial Data. SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the device. The SDA pin input
buffer is always active (not gated). This pin requires an external pull up resistor.
Ground.
Connection to other end of resistor for (the 100 Tap) DCP 1.
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 1.
Connection to end of resistor array for (the 100 Tap) DCP 1.
Connection to end of resistor array for (the 64 Tap) Digitally Controlled Potentiometer (DCP) 0.
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 0.
Connection to the other end of resistor array for (the 64 Tap) DCP 0.
V2 Voltage Monitor Input. V2 is the input to a non-inverting voltage comparator circuit. When the V2 input is greater than the
V
V2 RESET Output. This open drain output makes a transition to a HIGH level when V2 is greater than V
when V2 is less than V
external “pull-up” resistor.
TRIP3
TRIP2
threshold voltage, V3RO makes a transition to a HIGH level. Connect V3 to V
threshold voltage, V2RO makes a transition to a HIGH level. Connect V2 to V
3
TRIP2
. There is no power-up reset delay circuitry on this pin. The V2RO pin requires the use of an
V3RO
R
SCL
SDA
R
V
R
WP
MR
W2
V3
SS
H2
L2
NOT TO SCALE
(20 LD TSSOP)
10
1
2
3
4
6
7
8
9
5
TOP VIEW
X9520
X9520
20
19
18
17
16
15
14
13
12
11
FUNCTION
V1/VCC
V1RO
V2RO
V2
R
R
R
R
R
R
purst
W0
W1
L0
H0
H1
L1
after MR has returned to it’s normally LOW state. The
SS
SS
when not used.
when not used.
TRIP2
TRIP3
, and goes LOW
and goes LOW
August 20, 2007
FN8206.2