tb62300fg TOSHIBA Semiconductor CORPORATION, tb62300fg Datasheet - Page 19

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tb62300fg

Manufacturer Part Number
tb62300fg
Description
Dual Full-bridge Driver For Dc Motor
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
Power Supply Sequence
Note 1: If V
Note 2: When the V
Note 3: Since V
V
V
Internal reset
SLEEP input
(Note1)
DD
M
internally reset.
This is a protective measure against malfunction. Likewise, if V
regulation voltage is applied to V
To avoid malfunction, when turning on V
recommended.
It takes time for the output control charge pump circuit to stabilize. Wait up to t
before driving a motor.
such a case, the charge pump circuit cannot operate properly because of insufficient voltage. The IC should
be held in SLEEP mode until V
At that time, a current of several mA flows due to a current path between V
When the output voltage is high, make sure that the specified voltage is applied to V
DD
drops to the level of the V
DD
V
V
V
GND
V
V
V
GND
Non-reset
Reset
DD (max)
DD (min)
DDR
M
M (min)
MR
= 0 V and V
M
value is between 3.3 to 5.5 V, the internal reset is released, thus output may be active. In
H
L
(Recommended)
M
= voltage within the rating are applied, output is turned off by internal reset.
M
DDR
DD
reaches 13 V or more.
, the IC is internally reset as a protective measure against malfunction.
or below while the specified voltage is applied to the V
M
or V
Takes up to t
19
DD
, applying a signal to the SLEEP pin at the above timing is
Non-operable area
ONG
until operable
M
drops to the level of V
M
and V
ONG
DD
time after power on
DD
.
.
MR
TB62300FG
or below while
M
2005-04-04
pin, the IC is

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