lm27342sdx National Semiconductor Corporation, lm27342sdx Datasheet - Page 12

• Manufacturer Part Number: lm27342sdx
• Description: 2 Mhz 1.5a/2a Wide Input Range Step-down Dc-dc Regulator With Frequency Synchronization
• Manufacturer: National Semiconductor Corporation

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FREQUENCY SYNCHRONIZATION
The LM27341/LM27342 switching frequency can be synchro-
nized to an external clock, between 1.00 and 2.35 MHz,
applied at the SYNC pin. At the first rising edge applied to the
SYNC pin, the internal oscillator is overridden and subse-
quent positive edges will initiate switching cycles. If the ex-
ternal SYNC signal is lost during operation, the LM27341/
LM27342 will revert to its internal 2 MHz oscillator within 1.5
µs. To disable Frequency Synchronization and utilize the in-
ternal 2 MHz oscillator, connect the SYNC pin to GND.
The SYNC pin gives the designer the flexibility to optimize
their design. A lower switching frequency can be chosen for
higher efficiency. A higher switching frequency can be chosen
to keep EMI out of sensitive ranges such as the AM radio
band. Synchronization can also be used to eliminate beat fre-
quencies generated by the interaction of multiple switching
power converters. Synchronizing multiple switching power
converters will result in cleaner power rails.
The selected switching frequency (f
on-time (t
vice.
Operation below D
LM27342 will skip pulses to keep the output voltage in regu-
lation, and the current limit is not guaranteed. The switching
is in phase but no longer at the same switching frequency as
the SYNC signal.
CURRENT LIMIT
The LM27341 and LM27342 use cycle-by-cycle current lim-
iting to protect the output switch. During each switching cycle,
a current limit comparator detects if the output switch current
exceeds 2.0A min (LM27341) or 2.5A min (LM27342) , and
turns off the switch until the next switching cycle begins.
FREQUENCY FOLDBACK
The LM27341/LM27342 employs frequency foldback to pro-
tect the device from current run-away during output short-
circuit. Once the FB pin voltage falls below regulation, the
switch frequency will smoothly reduce with the falling FB volt-
age until the switch frequency reaches 220 kHz (typ). If the
device is synchronized to an external clock, synchronization
is disabled until the FB pin voltage exceeds 0.53V
SOFT-START
The LM27341/LM27342 has a fixed internal soft-start of 1 ms
(typ). During soft-start, the error amplifier’s reference voltage
ramps from 0.0 V to its nominal value of 1.0 V in approximately
1 ms. This forces the regulator output to ramp in a controlled
fashion, which helps reduce inrush current. Upon soft-start
the part will initially be in frequency foldback and the frequen-
cy will rise as FB rises. The regulator will gradually rise to 2
MHz. The LM27341/LM27342 will allow synchronization to an
external clock at FB > 0.53V.
OUTPUT OVERVOLTAGE PROTECTION
The overvoltage comparator turns off the internal power
NFET when the FB pin voltage exceeds the internal reference
voltage by 13% (V
turned off the output voltage will decrease toward the regula-
tion level.
UNDERVOLTAGE LOCKOUT
Undervoltage lockout (UVLO) prevents the LM27341/
LM27342 from operating until the input voltage exceeds
2.75V(typ).
MIN
) limit the minimum duty cycle (D
FB
MIN
D
> 1.13 * V
MIN
is not reccomended. The LM27341/
= t
MIN
x f
REF
SYNC
). With the power NFET
SYNC
) and the minimum
MIN
) of the de-
12
The UVLO threshold has approximately 470 mV of hysteresis,
so the part will operate until V
teresis prevents the part from turning off during power up if
V
THERMAL SHUTDOWN
Thermal shutdown limits total power dissipation by turning off
the internal NMOS switch when the IC junction temperature
exceeds 165°C (typ). After thermal shutdown occurs, hys-
teresis prevents the internal NMOS switch from turning on
until the junction temperature drops to approximately 150°C.
Design Guide
INDUCTOR SELECTION
Inductor selection is critical to the performance of the
LM27341/LM27342. The selection of the inductor affects sta-
bility, transient response and efficiency. A key factor in induc-
tor selection is determining the ripple current (Δi
2).
The ripple current (Δi
First, by allowing more ripple current, lower inductance values
can be used with a corresponding decrease in physical di-
mensions and improved transient response. On the other
hand, allowing less ripple current will increase the maximum
achievable load current and reduce the output voltage ripple
(see Output Capacitor section for more details on calculating
output voltage ripple). Increasing the maximum load current
is achieved by ensuring that the peak inductor current (I
never exceeds the minimum current limit of 2.0A min
(LM27341) or 2.5A min (LM27342) .
Secondly, the slope of the ripple current affects the current
control loop. The LM27341/LM27342 has a fixed slope cor-
rective ramp. When the slope of the current ripple becomes
significantly less than the converter’s corrective ramp (see
Figure 1), the inductor pole will move from high frequencies
to lower frequencies. This negates one advantage that peak
current-mode control has over voltage-mode control, which
is, a single low frequency pole in the power stage of the con-
verter. This can reduce the phase margin, crossover frequen-
cy and potentially cause instability in the converter. Contrarily,
when the slope of the ripple current becomes significantly
greater than the converter’s corrective ramp, resonant peak-
ing can occur in the control loop. This can also cause insta-
bility (Sub-Harmonic Oscillation) in the converter. For the
power supply designer this means that for lower switching
frequencies the current ripple must be increased to keep the
inductor pole well above crossover. It also means that for
higher switching frequencies the current ripple must be de-
creased to avoid resonant peaking.
With all these factors, how is the desired ripple current se-
lected? The ripple ratio (r) is defined as the ratio of inductor
ripple current (Δi
imum load:
A good compromise between physical size, transient re-
sponse and efficiency is achieved when we set the ripple ratio
between 0.2 and 0.4. The recommended ripple ratio vs. duty
cycle shown below (see Figure 6) is based upon this com-
promise and control loop optimizations. Note that this is just
IN
has finite impedance.
L
) to output current (I
I
L
LPK
) is important in many ways.
= I
OUT
IN
drops below 2.28V(typ). Hys-
+ Δi
L
OUT
/ 2
), evaluated at max-
L
) (see Figure
LPK
)