lm27965sqx-m National Semiconductor Corporation, lm27965sqx-m Datasheet - Page 8

• Manufacturer Part Number: lm27965sqx-m
• Description: Dual Display White Led Driver With I2c Compatible Brightness Control
• Manufacturer: National Semiconductor Corporation

www.national.com
Circuit Description
OVERVIEW
The LM27965 is a white LED driver system based upon an
adaptive 3/2× - 1× CMOS charge pump capable of supplying
up to 180mA of total output current. With three separately
controlled banks of constant current sinks, the LM27965 is an
ideal solution for platforms requiring a single white LED driver
for main display, sub display, and indicator lighting. The tightly
matched current sinks ensure uniform brightness from the
LEDs across the entire small-format display.
Each LED is configured in a common anode configuration,
with the peak drive current being programmed through the
use of an external R
is used to enable the device and vary the brightness within
the individual current sink banks. For BankA and BankB, 32
levels of brightness control are available. The brightness con-
trol is achieved through a mix of analog and pulse width
modulated (PWM) methods. BankC has 4 analog brightness
levels available.
CIRCUIT COMPONENTS
Charge Pump
The input to the 3/2× - 1x charge pump is connected to the
V
nected to the V
range of the LM27965 is 3.0V to 5.5V. The device’s regulated
charge pump has both open loop and closed loop modes of
operation. When the device is in open loop, the voltage at
V
the device is in closed loop, the voltage at V
to 4.6V (typ.). The charge pump gain transitions are actively
selected to maintain regulation based on LED forward voltage
and load requirements.
LED Forward Voltage Monitoring
The LM27965 has the ability to switch converter gains (1x or
3/2x) based on the forward voltage of the LED load. This abil-
ity to switch gains maximizes efficiency for a given load.
Forward voltage monitoring occurs on all diode pins within
BankA and BankB. At higher input voltages, the LM27965 will
operate in pass mode, allowing the P
input voltage. As the input voltage drops, the voltage on the
DXX pins will also drop (V
the active Dxx pins reaches a voltage approximately equal to
175mV, the charge pump will switch to the gain of 3/2. This
switch-over ensures that the current through the LEDs never
becomes pinched off due to a lack of headroom across the
current sinks.
Only active Dxx pins will be monitored. For example, if only
BankA is enabled, the LEDs in BankB will not affect the gain
transition point. If both banks are enabled, all diodes will be
monitored, and the gain transition will be based upon the
diode with the highest forward voltage. Diode pins D5A and
D3B can have the diode sensing circuity disabled through the
general purpose register if those drivers are not going to be
used.
BankC (D1C) is not a monitored LED current sink.
RESETPin
The LM27965 has a hardware reset pin (RESET) that allows
the device to be disabled by an external controller without re-
quiring an I
RESET pin should be held high (logic '1') to prevent an un-
wanted reset. When the RESET is driven low (logic '0'), all
IN
OUT
pin, and the regulated output of the charge pump is con-
is equal to the gain times the voltage at the input. When
2
C write command. Under normal operation, the
OUT
SET
pin. The recommended input voltage
resistor. An I
DXX
= V
POUT
2
OUT
C compatible interface
– V
voltage to track the
LEDx
OUT
). Once any of
is regulated
8
internal control registers reset to the default states and the
part becomes disabled. Please see the Electrical Character-
istics section of the datasheet for required voltage thresholds.
I
DATA VALIDITY
The data on SDIO line must be stable during the HIGH period
of the clock signal (SCL). In other words, state of the data line
can only be changed when CLK is LOW.
A pull-up resistor between VIO and SDIO must be greater
than [ (VIO-V
Using a larger pull-up resistor results in lower switching cur-
rent with slower edges, while using a smaller pull-up results
in higher switching currents with faster edges.
START AND STOP CONDITIONS
START and STOP conditions classify the beginning and the
end of the I
signal transitioning from HIGH to LOW while SCL line is
HIGH. A STOP condition is defined as the SDIO transitioning
from LOW to HIGH while SCL is HIGH. The I
generates START and STOP conditions. The I
sidered to be busy after a START condition and free after a
STOP condition. During data transmission, the I
can generate repeated START conditions. First START and
repeated START conditions are equivalent, function-wise.
TRANSFERING DATA
Every byte put on the SDIO line must be eight bits long, with
the most significant bit (MSB) transferred first. Each byte of
data has to be followed by an acknowledge bit. The acknowl-
edge related clock pulse is generated by the master. The
master releases the SDIO line (HIGH) during the acknowl-
edge clock pulse. The LM27965 pulls down the SDIO line
during the 9th clock pulse, signifying an acknowledge. The
LM27965 generates an acknowledge after each byte is re-
ceived.
After the START condition, the I
dress. This address is seven bits long followed by an eighth
bit which is a data direction bit (R/W). The LM27965 address
is 36h (38h for -M version). For the eighth bit, a “0” indicates
a WRITE and a “1” indicates a READ. The second byte se-
2
C Compatible Interface
FIGURE 2. Start and Stop Conditions
2
C session. A START condition is defined as SDIO
FIGURE 1. Data Validity Diagram
OL
) / 3mA] to meet the V
2
C master sends a chip ad-
OL
requirement on SDIO.
2
C master always
2
C bus is con-
2
C master
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