lm2746mxax National Semiconductor Corporation, lm2746mxax Datasheet - Page 17

• Manufacturer Part Number: lm2746mxax
• Description: Low Voltage N-channel Mosfet Synchronous Buck Regulator Controller
• Manufacturer: National Semiconductor Corporation

Application Information
One popular method for selecting the compensation compo-
nents is to create Bode plots of gain and phase for the power
stage and error amplifier. Combined, they make the overall
bandwidth and phase margin of the regulator easy to see.
Software tools such as Excel, MathCAD, and Matlab are
useful for showing how changes in compensation or the
power stage affect system gain and phase.
The power stage modulator provides a DC gain A
equal to the input voltage divided by the peak-to-peak value
of the PWM ramp. This ramp is 1.0VP-P for the LM2746. The
inductor and output capacitor create a double pole at fre-
quency f
single zero at frequency f
3.3V, these quantities are:
In the equation for f
resistance, and represents the inductor DCR plus the on
resistance of the top power MOSFET. R
voltage divided by output current. The power stage transfer
function G
13 shows Bode plots of the phase and gain in this example.
FIGURE 12. Power Stage and Error Amp
DP
PS
, and the capacitor ESR and capacitance create a
is given by the following equation, and Figure
DP
, the variable R
ESR
. For this example, with V
L
is the power stage
(Continued)
O
is the output
DC
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that is
IN
=
17
a = LC
b = L + C
c = R
The double pole at 4.5kHz causes the phase to drop to
approximately -130˚ at around 10kHz. The ESR zero, at
20.3kHz, provides a +90˚ boost that prevents the phase from
dropping to -180
bandwidth would be approximately 10kHz and the phase
margin 53˚. In theory, the loop would be stable, but would
suffer from poor DC regulation (due to the low DC gain) and
would be slow to respond to load transients (due to the low
bandwidth.) In practice, the loop could easily become un-
stable due to tolerances in the output inductor, capacitor, or
changes in output current, or input voltage. Therefore, the
loop is compensated using the error amplifier and a few
passive components.
For this example, a Type III, or three-pole-two-zero approach
gives optimal bandwidth and phase.
In most voltage mode compensation schemes, including
Type III, a single pole is placed at the origin to boost DC gain
O
O
FIGURE 13. Power Stage Gain and Phase
+ R
(R
O
O
(R
L
+ R
O
R
C
L
o
. If this loop were left uncompensated, the
)
+ R
O
R
C
+ R
C
R
L
)
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