tle4997i Infineon Technologies Corporation, tle4997i Datasheet - Page 28

• Manufacturer Part Number: tle4997i
• Description: Programmable Linear Hall Sensor For Industrial Use
• Manufacturer: Infineon Technologies Corporation

TLE4997I
Calibration
9.1
Calibration Data Memory
When the MEMLOCK bits are programmed (two redundant bits), the memory content is
frozen and may not be changed anymore. Furthermore the programming interface is
locked out and the chip remains in the application mode only. This prevents accidentally
programming due to environmental influences.
Column Parity Bits
User-Calibration Bits
Pre-Calibration Bits
Figure 9
EEPROM Map
A matrix parity architecture allows the automatic correction of any single bit error.
Each row is protected by a row parity bit. The sum of bits set including this bit must be
an odd number (ODD PARITY).
Each column is additionally protected by a column parity bit. Each bit in the even
positions (0, 2, etc.) of all lines must sum up in an even number (EVEN PARITY), each
bit in the odd positions (1,3, etc.) must have an odd sum (ODD PARITY).
This mechanisms of different parity calculations protect also against many block errors
(like erasing a full line or even the whole EEPROM).
When modifying the application bits (like Gain, Offset, TC, etc.) the parity bits must be
updated. For the column bits, also the pre-calibration area must be read out and
considered for correct parity generation.
Note: A specific programming algorithm must be followed to ensure the data retention.
A detailed separate programming specification is available on request.
Preliminary Data Sheet
28
V 1.01, 2006-09