ncp360 ON Semiconductor, ncp360 Datasheet
ncp360
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ncp360 Summary of contents
Page 1
... USB Positive Overvoltage Protection Controller with Internal PMOS FET and Status FLAG NCP360 is able to disconnect the systems from its output pin in case wrong VBUS operating conditions is detected. The system is positive over-voltage protected up to +20 V. Thanks to this device using internal PMOS FET, no external device is necessary, reducing the system cost and the PCB area of the application board ...
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... OVLO threshold. Since the FLAG pin is open drain functionality, an external pull up resistor OUT OUTPUT Output Voltage Pin. The output is disconnected from the VBUS power supply when the input voltage is above OVLO threshold or below UVLO threshold capacitor must be connected to this pin. NCP360 PIN CONNECTIONS IN 6 FLAG GND 5 ...
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... INPUT X5R 0603 C1 Figure 1. Typical Application Circuit (UDFN Pinout) INPUT EN LDO NCP360 OUTPUT OUT 5 OUT X5R 0603 C2 NCP360 FLAG FLAG GND 2 Thermal Shutdown Soft Start UVLO V REF OVLO Figure 2. Functional Block Diagram http://onsemi.com 3 FLAG Power ...
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... EN TIMINGS Start Up Delay FLAG going up Delay Output Turn Off Time Alert Delay Disable Time Thermal Shutdown Temperature Thermal Shutdown Hysteresis T NOTE: Thermal Shutdown parameter has been fully characterized and guaranteed by design. NCP360 Symbol Vmin Vmin Vmax Vmax Imax TSOP-5 R UDFN ...
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... FLAG 1.2 V Figure 3. Start Up Sequence 1 dis V out 0 DS(on) FLAG Figure 5. Disable Voltage Detection IN Voltage Detection NCP360 <OVLO OVLO out in DS(on DS(on) FLAG Figure 4. Shutdown on Over Voltage Detection FLAG Figure 6. FLAG Response with OUT Figure 7 ...
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... Ch3 in out Figure 11. Output Turn Off Time V = Ch1 Ch2 in out Figure 13. Disable Time EN = Ch1 Ch2, FLAG = Ch3 out NCP360 Figure 10. FLAG Going Up Delay V = Ch3, FLAG = Ch2 out Figure 12. Alert Delay V = Ch1, FLAG = Ch3 out Figure 14. Thermal Shutdown V = Ch1 http://onsemi.com ...
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... V , INPUT VOLTAGE (V) in Figure 17. Supply Quiescent Current vs. V NCP360 450 400 350 300 250 200 150 100 50 0 -50 Figure 16 http://onsemi.com 3 ...
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... PCB Recommendations The NCP360 integrates a 500 mA rated PMOS FET, and the PCB rules must be respected to properly evacuate the heat out of the silicon. The UDFN PAD1 must be connected to ground plane to increase the heat transfer if necessary from an application standpoint. Of course, in any case, this pad shall be not connected to any other potential ...
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... 0. BOTTOM VIEW NCP360 PACKAGE DIMENSIONS UDFN6 2x2, 0.65P CASE 517AB-01 ISSUE B NOTES DIMENSIONING AND TOLERANCING PER B 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO THE EXPOSED E SOLDERING FOOTPRINT* A 0.95 SEATING C PLANE e 4X 1.70 ...
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... IN THIS LOCATION. TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2 FROM BODY. MILLIMETERS DIM MIN MAX A 3.00 BSC B 1.50 BSC C 0.90 1.10 D 0.25 0.50 G 0.95 BSC H 0.01 0.10 J 0.10 0.26 K 0.20 0.60 L 1.25 1. 2.50 3.00 2.4 0.094 mm inches ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your loca Sales Representative NCP360/D ...