hip4081ip Intersil Corporation, hip4081ip Datasheet - Page 12

• Manufacturer Part Number: hip4081ip
• Description: 80v/2.5a Peak, High Frequency Full Bridge Fet Driver
• Manufacturer: Intersil Corporation

Typical Performance Curves
HI4081 Power-up Application Information
The HIP4081 H-Bridge Driver IC requires external circuitry
to assure reliable start-up conditions of the upper drivers. If
not addressed in the application, the H-bridge power MOS-
FETs may be exposed to shoot-through current, possibly
leading to MOSFET failure. Following the instructions below
will result in reliable start-up.
The HIP4081 has four inputs, one for each output. Outputs
ALO and BLO are directly controlled by input ALI and BLI.
By holding ALI and BLI low during start-up no shoot-through
conditions can occur. To set the latches to the upper drivers
such that the driver outputs, AHO and BHO, are off, the DIS
pin must be toggled from low to high after power is applied.
This is accomplished with a simple resistor divider, as shown
below in Figure 30. As the V
up, the DIS voltage is below its input threshold of 1.7V due
to the R1/R2 resistor divider. When V
approximately 9V to 10V, DIS becomes greater than the
input threshold and the chip disables all outputs. It is critical
that ALI and BLI be held low prior to DIS reaching its thresh-
old level of 1.7V while V
through is avoided. After power is up the chip can be
enabled by the ENABLE signal which pulls the DIS pin low.
FIGURE 28. HIGH VOLTAGE LEVEL-SHIFT CURRENT vs
1000
500
200
100
50
20
10
5
2
1
1
FREQUENCY AND BUS VOLTAGE
2
5
SWITCHING FREQUENCY (kHz)
DD
10
/V
DD
20
CC
/V
is ramping up, so that shoot
CC
80V
60V
40V
20V
50
supply ramps from zero
100
R
V
DD
HDEL
DD
200
/V
= V
CC
= R
CC
500
LDEL
exceeds
= V
AHB
1000
HIP4081
= 100K and T
= V
12
BHB
NOTES:
2. ALI and/or BLI may be high after t1, whereupon the ENABLE pin
3. Another product, HIP4081A, incorporates undervoltage circuitry
150
120
ALI, BLI
FIGURE 29. MINIMUM DEAD-TIME vs DEL RESISTANCE
90
60
30
= 12V, V
may also be brought high.
which eliminates the need for the above power up circuitry.
0
A
10
FIGURE 30B. TIMING DIAGRAM FOR FIGURE 30A
V
= 25
DIS
DD
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
ENABLE
o
SS
C, Unless Otherwise Specified (Continued)
50
= V
t1
ALS
1.7V
8.5V TO 10.5V (ASSUMES 5% RESISTORS)
3.3K
15K
R1
R2
HDEL/LDEL RESISTANCE (k )
= V
FIGURE 30A.
BLS
100
= V
10
1 BHB
2
3
4
5
6
7
8
9
12V, FINAL VALUE
AHS
BHI
DIS
V
BLI
ALI
AHI
HDEL
LDEL
AHB
SS
150
= V
BHS
BHO
AHO
BHS
BLO
ALO
AHS
BLS
V
V
ALS
DD
CC
= 0V,
20
19
18
17
16
15
14
13
12
11
200
250