hip6007 Intersil Corporation, hip6007 Datasheet - Page 7

• Manufacturer Part Number: hip6007
• Description: Buck Pulse-width Modulator Pwm Controller
• Manufacturer: Intersil Corporation

Feedback Compensation
Figure 7 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(Vout) is regulated to the Reference voltage level. The error
amplifier (Error Amp) output (V
oscillator (OSC) triangular wave to provide a pulse-width
modulated (PWM) wave with an amplitude of Vin at the
PHASE node. The PWM wave is smoothed by the output
filter (Lo and Co).
The modulator transfer function is the small-signal transfer
function of Vout/V
Gain and the output filter (Lo and Co), with a double pole
break frequency at F
the modulator is simply the input voltage (Vin) divided by the
peak-to-peak oscillator voltage ∆V
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the HIP6007) and the impedance networks Z
and Z
a closed loop transfer function with the highest 0dB crossing
frequency (f
is the difference between the closed loop phase at f
F
LC =
FIGURE 7. VOLTAGE - MODE BUCK CONVERTER
∆V
OSC
FB
-------------------------------------- -
2π
. The goal of the compensation network is to provide
•
OSC
L
1
0dB
COMPARATOR
O
COMPENSATION DESIGN
ERROR
AMP
•
V
HIP6007
) and adequate phase margin. Phase margin
C
E/A
DETAILED COMPENSATION COMPONENTS
PWM
O
E/A
Z
+
-
COMP
FB
+
-
LC
C1
. This function is dominated by a DC
REFERENCE
and a zero at F
C2
+
-
R2
137
DRIVER
DRIVER
Z
REF
E/A
IN
) is compared with the
Z
OSC
FB
FB
V
F
IN
ESR
.
ESR
PHASE
C3
(PARASITIC)
. The DC Gain of
Z
=
R1
L
IN
O
------------------------------------------- -
2π
R3
ESR
•
C
V
O
(
OUT
ESR C
0dB
1
V
OUT
•
and
IN
O
HIP6007
)
180
network’s poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 8. Use these guidelines for
locating the poles and zeros of the compensation network:
Compensation Break Frequency Equations
Figure 8 shows an asymptotic plot of the DC-DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak do to the high Q factor of the output filter and is not
shown in Figure 8. Using the above guidelines should give a
Compensation Gain similar to the curve plotted. The open
loop error amplifier gain bounds the compensation gain.
Check the compensation gain at F
the error amplifier. The Closed Loop Gain is constructed on
the log-log graph of Figure 8 by adding the Modulator Gain (in
dB) to the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
compensation transfer function and plotting the gain.
The compensation gain uses external impedance networks
Z
overall loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
Include worst case component variations when determining
phase margin.
F
F
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1
3. Place 2
4. Place 1
5. Place 2
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
FB
Z1
Z2
100
-20
-40
-60
80
60
40
20
o
(~75% F
0
=
=
and Z
. The equations below relate the compensation
---------------------------------
2π R2 C1
---------------------------------------------------- -
2π
10
(R2/R1)
20LOG
•
•
MODULATOR
IN
(
ST
ND
ST
ND
1
R1 + R3
LC
to provide a stable, high bandwidth (BW)
100
•
Zero Below Filter’s Double Pole
Pole at the ESR Zero
1
Zero at Filter’s Double Pole
Pole at Half the Switching Frequency
)
GAIN
)
•
1K
F
C3
Z1
F
FREQUENCY (Hz)
LC
F
Z2
10K
F
P1
F
F
F
(V
ESR
P1
P2
P2
100K
IN
20LOG
F
/
=
=
∆
with the capabilities of
P2
V
----------------------------------------------------- -
2π R2
---------------------------------
2π R3
OSC
OPEN LOOP
ERROR AMP GAIN
•
•
1M
)
1
COMPENSATION
GAIN
•
•
CLOSED LOOP
GAIN
1


C3
--------------------- -
C1 + C2
C1 C2
10M
•


o
.