hip6016cb Intersil Corporation, hip6016cb Datasheet - Page 11

• Manufacturer Part Number: hip6016cb
• Description: Advanced Pwm And Dual Linear Power Control
• Manufacturer: Intersil Corporation

a closed loop transfer function with an acceptable 0dB
crossing frequency (f
Phase margin is the difference between the closed loop
phase at f
the compensation network’s poles, zeros and gain to the
components (R1, R2, R3, C1, C2, and C3) in Figure 11.
Use these guidelines for locating the poles and zeros of the
compensation network:
Compensation Break Frequency Equations
Figure 12 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual modulator gain has a peak due
to the high Q factor of the output filter at F
F Z1
F Z2
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1
3. Place 2
4. Place 1
5. Place 2
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if necessary
FIGURE 11. VOLTAGE-MODE BUCK CONVERTER
V
OSC
=
=
-----------------------------------
2
------------------------------------------------------ -
2
0dB
OSC
ST
ND
ST
ND
R2 C1
R1
1
ERROR
COMPENSATION DESIGN
AMP
and 180 degrees The equations below relate
Zero Below Filter’s Double Pole (~75% FLC)
Pole at the ESR Zero
HIP6016
Zero at Filter’s Double Pole
Pole at Half the Switching Frequency
+
V
1
E/A
R3
COMP
DETAILED FEEDBACK COMPENSATION
PWM
Z
+
-
COMP
0dB
+
-
FB
C1
REFERENCE
C3
) and adequate phase margin.
REFERENCE
2-206
C2
F P1
-
+
DRIVER
DRIVER
R2
F P2
Z
IN
=
------------------------------------------------------- -
2
=
Z
FB
FB
-----------------------------------
2
V
R 2
IN
PHASE
LC
C3
(PARASITIC)
R3 C3
1
1
, which is not
Z
R1
C1 C2
--------------------- -
C1
L
IN
O
ESR
R3
+
C2
C
V
O
OUT
V
OUT
HIP6016
shown in Figure 12. Using the above guidelines should yield a
compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at F
amplifier. The closed loop gain is constructed on the log-log
graph of Figure 12 by adding the modulator gain (in dB) to the
compensation gain (in dB). This is equivalent to multiplying
the modulator transfer function to the compensation transfer
function and plotting the gain.
The compensation gain uses external impedance networks
Z
control loop has a 0dB gain crossing with -20dB/decade slope
and a phase margin greater than 45 degrees. Include worst
case component variations when determining phase margin.
Component Selection Guidelines
Output Capacitor Selection
The output capacitors for each output have unique
requirements. In general the output capacitors should be
selected to meet the dynamic regulation requirements.
Additionally, the PWM converters require an output capacitor
to filter the current ripple. The linear regulator is internally
compensated and requires an output capacitor that meets
the stability requirements. The load transient for the
microprocessor core requires high quality capacitors to
supply the high slew rate (di/dt) current demands.
PWM Output Capacitors
Modern microprocessors produce transient load rates above
10A/ns. High frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors.
The bulk filter capacitor values are generally determined by
the ESR (effective series resistance) and ESL (effective series
inductance) parameters rather than actual capacitance.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
FIGURE 12. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
FB
100
-20
-40
-60
80
60
40
20
0
and Z
10
(R
20LOG
2
MODULATOR
IN
/R
1
to provide a stable, high bandwidth loop. A stable
)
GAIN
100
1K
F
Z1
P2
F
FREQUENCY (Hz)
LC
F
with the capabilities of the error
Z2
10K
F
F
P1
(V
ESR
IN
20LOG
100K
/ V
F
P2
OSC
OPEN LOOP
ERROR AMP GAIN
)
1M
COMPENSATION
CLOSED LOOP
10M
GAIN
GAIN