hip6502b Intersil Corporation, hip6502b Datasheet
hip6502b
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hip6502b Summary of contents
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... TM Data Sheet Multiple Linear Power Controller with ACPI Control Interface The HIP6502B complements either an HIP6020 or an HIP6021 in ACPI-compliant designs for microprocessor and computer applications. The IC integrates four linear controllers/regulators, switching, monitoring and control functions into a 20-pin SOIC package. One linear controller generates the 3 ...
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Block Diagram 12V 12V MONITOR 10.8V/9.8V TO 5VSB EA3 + - TO UV DETECTOR VSEN1 FAULT UV DETECTOR - + + UV COMPARATOR 3.75V - 5VDL GND 3V3DL 5V 3V3 3V3DLSB 5V MONITOR 4.5V/4.25V EA4 - + 3V3 MONITOR 2.97V/2.8V ...
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... MSEL SHUTDOWN 3 HIP6502B LINEAR LINEAR REGULATOR CONTROLLER LINEAR LINEAR CONTROLLER REGULATOR CONTROL HIP6502B LOGIC FIGURE 2. 12V 3V3 5VSB VSEN1 DRV2 5V VSEN2 3V3DLSB C OUT2 3V3DL VCLK HIP6502B C OUT4 FAULT S3 5VDLSB S5 DLA EN5VDL MSEL 5VDL GND FIGURE 3. Q1 2.5V MEM 2.5V V CLK 2. DUAL 5V ...
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... LINEAR REGULATOR (V MEM OUT2 Regulation VSEN2 Nominal Voltage Level VSEN2 Undervoltage Rising Threshold VSEN2 Output Current 4 HIP6502B Thermal Information Thermal Resistance (Typical, Note 1) SOIC Package +0.3V 12V Maximum Junction Temperature (Plastic Package .150 Maximum Storage Temperature Range . . . . . . . . . . -65 Maximum Lead Temperature (Soldering 10s .300 ...
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... High Level Input Threshold Low Level Input Threshold S3, S5 Internal Pull-up Impedance to 5VSB FAULT Output Impedance TEMPERATURE MONITOR Fault-Level Threshold (Note 4) Shutdown-Level Threshold (Note 4) NOTES Ambient Temperatures Less Than 50 3. Guaranteed by Correlation. 4. Guaranteed by Design. 5 HIP6502B SYMBOL TEST CONDITIONS I 5VSB = 5V DRV2 ) OUT3 V 3V3DL I 5VSB = 5V ...
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... FAULT (Pin 12) In case of an undervoltage on any of the outputs or on any of the monitored ATX outputs case of an overtemperature 6 HIP6502B event, this pin is used to report the fault condition by being pulled to 5VSB. SS (Pin 16) Connect this pin to a small ceramic capacitor (no less than 5nF ...
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... This pin is monitored for under-voltage events. Description Operation The HIP6502B controls 5 output voltages (Refer to Figures 1, 2, and 3 designed for microprocessor computer applications with 3.3V, 5V, 5VSB, and 12V bias input from an ATX power supply. The IC is composed of three linear controllers/regulators supplying the computer system’ ...
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... Additionally, the S3 pin features a 200 s delay in transitioning to sleep states. Once the S3 pin goes low, an internal timer is activated. At the end of the 200 s interval, if the S5 pin is low, the HIP6502B switches into S5 sleep state; if the S5 pin is high, the HIP6502B goes into S3 sleep state. 5VSB ...
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... SOFT-START INTO ACTIVE STATES (S0, S1) If both S3 and S5 are logic high at the time the 5VSB is applied, the HIP6502B will assume active state wake-up and keep off the controlled external transistors and the VCLK output until some time (typically 25ms) after the ATX’s main outputs used by the application (3 ...
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... Pulling the SS pin low effectively shuts down all the pass elements. Upon release of the SS pin, the HIP6502B undergoes a new soft-start cycle and resumes normal operation in accordance to the ATX supply and control pins status ...
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... Input Capacitors Selection The input capacitors for an HIP6502B application have to have a sufficiently low ESR as to not allow the input voltage to dip excessively when energy is transferred to the output capacitors. If the ATX supply does not meet the where ...
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... ATX’s outputs and the HIP6502B’s regulation levels could have as a result a brisk transfer of energy from the input capacitors to the supplied outputs. At the transition between active and sleep states, this phenomena could result in the 5VSB voltage dropping below the POR level (typically 4 ...
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... 12V 3V3 5VSB 5V VSEN1 + C5,16 2X150 F 3V3DLSB U1 HIP6502B 3V3DL C10 220 F FAULT EN5VDL MSEL C13 GND 0.1 F FIGURE 11. TYPICAL HIP6502B APPLICATION DIAGRAM + C2 220 DRV2 Q1 2SD1802 VSEN2 + C6,7 C8 2X150 VCLK C11 + C12 150 5VDLSB FDV304P DLA Q5 1/2 HUF76113DK8 ...
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... For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 14 HIP6502B M20.3 (JEDEC MS-013-AC ISSUE C) 20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE SYMBOL A ...