a29800tm-90i AMIC Technology Corporation, a29800tm-90i Datasheet - Page 6

• Manufacturer Part Number: a29800tm-90i
• Description: 1024k X 8 Bit / 512k X 16 Bit Cmos 5.0 Volt-only, Boot Sector Flash Memory
• Manufacturer: AMIC Technology Corporation

Word/Byte Configuration
The
operate in the byte or word configuration. If the
set at logic “1”, the device is in word configuration, I/O
are active and controlled by
If the
configuration, and only I/O
as an input for the LSB(A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive
the
selects the device.
data to the output pins.
during read operation. The internal state machine is set for
reading array data upon device power-up, or after a
hardware reset. This ensures that no spurious alteration of
the memory content occurs during the power transition. No
command is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid data
on the device data outputs. The device remains enabled for
read access until the command register contents are altered.
See "Reading Array Data" for more information. Refer to the
AC Read Operations table for timing specifications and to the
Read Operations Timings diagram for the timing waveforms,
l
current specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which includes
programming data to the device and erasing sectors of
memory), the system must drive
multiple sectors, or the entire device. The Sector Address
Tables indicate the address range that each sector occupies.
A "sector address" consists of the address inputs required to
uniquely select a sector. See the "Command Definitions"
section for details on erasing a sector or the entire chip, or
suspending/resuming the erase operation.
After the system writes the autoselect command sequence,
the device enters the autoselect mode. The system can then
read autoselect codes from the internal register (which is
separate from the memory array) on I/O
read cycle timings apply in this mode. Refer to the
"Autoselect Mode" and "Autoselect Command Sequence"
sections for more information.
I
current
Characteristics" section contains timing specification tables
and timing diagrams for write operations.
(November, 2007, Version 1.3)
CE
OE
CC1
CC2
and
CE
BYTE
in the DC Characteristics table represents the active
in the DC Characteristics table represents the active
to V
BYTE
and
OE
specification
IH
. An erase operation can erase one sector,
pin determines whether the I/O pins I/O
. I/O
OE
pin is set at logic “0”, the device is in byte
8
pins to V
- I/O
OE
14
WE
is the output control and gates array
for
are tri-stated, and I/O
0
IL
- I/O
CE
.
should remain at V
the
CE
7
and
are active and controlled by
write
is the power control and
WE
OE
and
.
mode.
7
- I/O
CE
15
IH
BYTE
0
pin is used
to V
all the time
. Standard
The
15
15
IL
- I/O
pin is
, and
- I/O
"AC
0
0
5
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status bits
on I/O
specifications apply. Refer to "Write Operation Status" for
more information, and to each AC Characteristics section for
timing diagrams.
Standby Mode
When the system is not reading or writing to the device, it
can place the device in the standby mode. In this mode,
current consumption is greatly reduced, and the outputs are
placed in the high impedance state, independent of the
input.
The device enters the CMOS standby mode when the
more restricted voltage range than V
the TTL standby mode when
standard access time (t
If the device is deselected during erasure or programming,
the device draws active current until the operation is
completed.
I
current specification.
Output Disable Mode
When the
disabled. The output pins are placed in the high impedance
state.
The RESET pin provides a hardware method of resetting
the device to reading array data. When the system drives the
immediately terminates any operation in progress, tristates
all data output pins, and ignores all read/write attempts for
the duration of the RESET pulse. The device also resets the
internal state machine to reading array data. The operation
that was interrupted should be reinitiated once the device is
ready to accept another command sequence, to ensure data
integrity.
The RESET pin may be tied to the system reset circuitry. A
system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from the
Flash memory.
Refer to the AC Characteristics tables for RESET
parameters and diagram.
RESET pins are both held at V
RESET is held at VCC±0.5V. The device requires the
RESET
RESET pin low for at least a period of t
CC3
in the DC Characteristics tables represents the standby
7
- I/O
: Hardware Reset Pin
OE
0
. Standard read cycle timings and I
input is at V
CE
) before it is ready to read data.
AMIC Technology, Corp.
IH
CC
, output from the device is
CE
± 0.5V. (Note that this is a
A29800 Series
IH
is held at V
.) The device enters
RP
, the device
IH
CC
, while
CE
read
OE
&