t6817-tksy ATMEL Corporation, t6817-tksy Datasheet - Page 4

no-image

t6817-tksy

Manufacturer Part Number
t6817-tksy
Description
T6817 Dual Triple Dmos Output Driver With Serial Input Control
Manufacturer
ATMEL Corporation
Datasheet
3. Functional Description
3.1
Figure 3-1.
4
Serial Interface
CS
DI
CLK
DO
T6817
Data Transfer Input Data Protocol
TP
SRR
0
SLS1 SHS1 SLS2 SHS2 SLS3 SHS3
1
LS1
Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized
to CLK and are accepted on the falling edge of the CLK signal. LSB (bit 0, SRR) has to be trans-
ferred first. Execution of new input data is enabled on the rising edge of the CS signal. When CS
is high, pin DO is in tri-state condition. This output is enabled on the falling edge of CS. Output
data will change their state with the rising edge of CLK and stay stable until the next rising edge
of CLK appears. LSB (bit 0, TP) is transferred first.
Table 3-1.
Bit
10
11
12
13
14
15
2
0
1
2
3
4
5
6
7
8
9
HS1
3
LS2
Input Register
Input Data Protocol
SRR
HS1
HS2
HS3
OLD
SCT
4
LS1
LS2
LS3
n.u.
n.u.
n.u.
n.u.
n.u.
n.u.
HS2
SI
5
LS3
6
HS3
Function
Status register reset (high = reset; the bits PSF, SCD and overtemperature
shutdown in the output data register are set to low)
Controls output LS1 (high = switch output LS1 on)
Controls output HS1 (high = switch output HS1 on)
See LS1
See HS1
See LS1
See HS1
Not used
Not used
Not used
Not used
Not used
Not used
Open load detection (low = on)
Programmable time delay for short circuit and overvoltage shutdown (short
circuit shutdown delay high/low = 100 ms/12.5 ms, overvoltage shutdown
delay high/low = 14 ms/3.5 ms
Software inhibit; low = standby, high = normal operation
(data transfer is not affected by standby function because the digital part is
still powered)
7
n.u.
n.u.
8
n.u.
n.u.
9
n.u.
n.u.
10
n.u.
n.u.
11
n.u.
n.u.
12
n.u.
n.u.
13
SCD
OLD
14
SCT
INH
15
PSF
SI
4670D–BCD–04/07

Related parts for t6817-tksy