r2j20601np Renesas Electronics Corporation., r2j20601np Datasheet
r2j20601np
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r2j20601np Summary of contents
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... Driver – MOS FET Integrated SiP (DrMOS) Description The R2J20601NP multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a single QFN package. The on and off timing of the power MOS FET is optimized by the built-in driver, making this device suitable for large-current buck converters. The chip also incorporates a high-side bootstrap Schottky barrier diode (SBD), eliminating the need for an external SBD for this purpose ...
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... R2J20601NP Block Diagram DISBL# 2 µA CGND VCIN Input logic PWM (TTL level) (3 state in) CGND Notes: 1. Truth table for the DISBL# pin. DISBL# Input Driver Chip Status “L” Shutdown (GL “L”) “Open” Shutdown (GL “L”) “H” Enable (GL “Active”) 2. Output signal from the UVL block " ...
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... R2J20601NP Pin Arrangement 14 13 VIN 15 VIN 16 VIN 17 VIN 18 VIN 19 VIN 20 VSWH 21 PGND 22 PGND 23 PGND 24 PGND 25 PGND 26 PGND 27 PGND Pin Description Pin Name Pin No. CGND 1, 6, 51, Tab Control signal ground connect VLDRV 3 Low side gate supply voltage VCIN 4 Control input voltage (+12 V input) ...
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... R2J20601NP Absolute Maximum Ratings Item Power dissipation Average output current Input voltage Supply voltage Low side driver voltage Switch node voltage BOOT voltage DISBL# voltage PWM voltage Reg5V current Operating junction temperature Storage temperature Notes: 1. Pt(25) represents a PCB temperature of 25° C, and Pt(100) represents 100 C. ...
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... R2J20601NP Electrical Characteristics ( VCIN = 12 V, VLDRV = 5 V, VSWH = 0 V, unless otherwise specified) Item Supply VCIN start threshold VCIN shutdown threshold UVLO hysteresis VCIN bias current VLDRV bias current PWM PWM rising threshold Input PWM falling threshold PWM input resistance Tri-state shutdown window ...
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... R2J20601NP Typical Application + +12 V PWM1 PWM PWM2 control circuit PWM3 PWM4 Rev.5.00 Apr 10, 2006 page VCIN VLDRV BOOT DISBL# VIN Reg5V DrMOS VSWH PWM PGND CGND GH GL VCIN VLDRV BOOT DISBL# VIN DrMOS Reg5V VSWH PWM PGND ...
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... R2J20601NP Test Circuit LDRV VLDRV A I CIN VCIN A DISBL# Reg5V 5 V pulse PWM Note × × LDRV LDRV × V OUT O O Efficiency = OUT IN P (DrMOS – P LOSS IN OUT Rev.5.00 Apr 10, 2006 page ...
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... R2J20601NP Typical Data Power Loss vs. Output Current 9 VIN = 12 V VCIN = VLDRV = 5 V VOUT = 1 fpwm = 1 MHz 0.45 µ Output Current (A) Power Loss vs. Output Voltage VIN = 12 V VCIN = VLDRV = 5 V fpwm = 1 MHz L = 0.45 µ ...
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... R2J20601NP Typical Data (cont.) Power Loss vs. Output Inductance VIN = 12 V VCIN = 12 V VLDRV = VOUT = 1.3 V fpwm = 1 MHz 0.1 0.2 0.3 0.4 0.5 0.6 Output Inductance (µH) Average ILDRV vs. Switching Frequency 200 VIN = 12 V VCIN = 12 V VOUT = 1.3 V 160 IOUT = 0.45 µH 120 250 500 750 ...
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... R2J20601NP Description of Operation The DrMOS multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a single QFN package. Since the parasitic inductance between each chip is extremely small, the module is highly suitable for use in buck converters to be operated at high frequencies. The control timing between the high-side MOS FET, low-side MOS FET, and driver is optimized so that high efficiency can be obtained at low output-voltage ...
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... R2J20601NP The PWM input is TTL level and has hysteresis. When the PWM input signal is abnormal, e.g., when the signal route from the control IC is abnormal, the tri-state function turns off the high- and low-side MOS FETs. This function operates when the PWM input signal stays in the input hysteresis window for 240 ns (typ.). After the tri-state mode has been entered and GH and GL have become low, a PWM input voltage of 3 ...
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... The GH and GL pins are the gate-monitor pins for each MOS FET. MOS FETs The MOS FETs incorporated in R2J20601NP are highly suitable for synchronous-rectification buck conversion. For the high-side MOS FET, the drain is connected to the VIN pin and the source is connected to the VSWH pin. For the low-side MOS FET, the drain is connected to the VSWH pin and the source is connected to the PGND pin ...
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... R2J20601NP Package Dimensions JEITA Package Code RENESAS Code P-HWQFN56-8x8-0.50 PWQN0056KA Rev.5.00 Apr 10, 2006 page Previous Code MASS[Typ.] TNP-56TV 0.17g 0.85 3.55 0.55 2. × Ni/Pd/Au plating ) 0. Dimension in Millimeters Reference Symbol ...
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Sales Strategic Planning Div. Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble ...