r2j20751np Renesas Electronics Corporation., r2j20751np Datasheet
r2j20751np
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r2j20751np Summary of contents
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... R2J20751NP Peak Current Mode Synchronous Buck Controller with Power MOS FETs Description This all-in-one SiP for POL (point-of-load) applications is a multi-chip module incorporating a high-side MOS FET, low-side MOS FET, and PWM controller in a single QFN package. The on and off timing of the power MOS FET is optimized by the built-in driver circuit, making this device suitable for large-current high-efficiency buck converters ...
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... R2J20751NP Application Circuit Example VCIN ON/OFF PGOOD TRK-SS FB EO/CO REFIN SGND R07DS0240EJ0100 Rev.1.00 Jan 26, 2011 VCIN (4.5V to 5.5V) Controller Chip Preliminary VIN (3.3V to 27V) VOUT (1.5V) SW Page ...
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... R2J20751NP Block Diagram R07DS0240EJ0100 Rev.1.00 Jan 26, 2011 Preliminary Page ...
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... R2J20751NP Pin Arrangement 10 OUT SGND 13 CLK 14 BOOT VIN 17 VIN 18 VIN 19 VIN 20 21 Package: QFN40 pin (6 mm R07DS0240EJ0100 Rev.1.00 Jan 26, 2011 SGND VIN Top view 6 mm, 0.5-mm pin pitch) Preliminary TRK-SS 39 SGND ...
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... R2J20751NP Pin Description Pin Name Pin No. VIN Input voltage for buck converter. SW 16, 25 Switching node. Connect a choke coil between the SW pin and dc output node of the converter. PGND Ground of the power stage. SGND 10, 13, 38 Ground of the IC chip. VCIN 6 Input voltage for control circuit ...
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... R2J20751NP Absolute Maximum Ratings Item Power dissipation Average output current Input voltage Supply voltage Switch node voltage BOOT pin voltage ON/OFF pin voltage PGOOD voltage Other pins voltage TRK-SS dc current IREF current EO sink current CO sink current CO source current Operating junction temperature Storage temperature Notes: 1. Pt(25) represents a PCB temperature of 25° ...
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... R2J20751NP Electrical Characteristics Item Supply VCIN start threshold VCIN shutdown threshold UVLO hysteresis Input bias current Slave standby current Input shutdown current Remote Disable threshold On/off Enable threshold Input current Reference IREF pin voltage current generator Oscillator CT oscillating frequency CT higher trip voltage ...
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... R2J20751NP Item Over- OVP trip voltage voltage Pre-OVP trip voltage protection Slope Slope current generator Clock Clock frequency generator OUT high voltage OUT low voltage IN input bias current IN input threshold IN input hysteresis Note: 1. Reference values for design. Not 100% tested in production. ...
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... R2J20751NP Description of Operation Peak Current Control The control IC operates as current programmed control mode, in which output of the converter is controlled by the choice of the peak current from the high-side MOS FET. The current from this MOS FET is sensed by an active current sensing circuit (ACS), the output current of which is 1/13700 (50 ppm) of the MOS FET current. The ACS current is then converted to certain voltage by external resistor on the CS pin ...
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... MOS FET remains in this state until VCIN is resupplied. Multi Phase Operation The R2J20751NP is a scalable solution. Pulling the FB pin of a device up to VCIN causes the device to operate as a slave. Clock timing is synchronized by connecting the CLK and CT pins of all devices. Current sharing is available by connecting the Share pins ...
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... R2J20751NP Output Voltage Setting The error amplifier of the device has an accurate 0.6 V reference voltage and REFIN pin which can input reference voltage from external voltage. When reference voltage is 0.6 V, feedback loop leads to the FB pin a voltage of 0 case of stable condition on the converter. Therefore the output voltage is; ...
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... R2J20751NP Rf Vout Design example; Specification 470 nH 600 F, Fsw = 500 kHz, Vin = 5 V, Vout = 1 k kΩ, RCS = 820 Ω 1. Flat band gain of error amplifier The flat band gain is (R1 // R2) {R2 / (R1 + R2)} Hence Af (R1 // R2) / {R2 / (R1 + R2)} ......(1) In the Bode plot, the total gain should be lower than 1 (0 dB) at the switching frequency. The total gain at Fsw (= Asw) depends on the flat-band gain should be expressed as follows ...
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... R2J20751NP equation (3), Nt/RCS SQRT {Vin 8 L 13700 / 820 = 2 SQRT { 470 nH 19.63 = SQRT {3.955} = 9.871 The frequency of the pole established by the power stage and modulator Co RCS A0) ......(5) Thus 13700 / (2 600 F 820 9.871) = 448.967 Hz Thus, Fzero = 10 ...
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... R2J20751NP Study of Vout Accuracy The nominal output voltage is calculated as Vout = VFB ( ......(6) Here, the typical FB voltage is 0 The accuracy of Vout is strongly dependent on the variation of VFB, R1 and R2. VFB has variation of 1% and resistance intrinsically has a certain variation. When we take the variation in resistance into account, equation (6) is extended to produce equation (7) ...
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... R2J20751NP The accuracy of Vout can be estimated by using equation (10). For Example, if Vout (typical) = 1.5 V, resistance variation is 1% (i.e K1 1.01 and 0.99), and VFB = 588 mV to 612 mV. Vout VFB = Vout (typical) Vout (typical) 612 3.23% or 588 3.16% Therefore, the output accuracy will be 3.2% under the above conditions. ...
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... R2J20751NP Timing Chart Peak Current Control Max. Duty (Internal signal) RES (Internal signal) TLD 50 ns (typ VIN Note: Propagation delay is ignored. R07DS0240EJ0100 Rev.1.00 Jan 26, 2011 EO (EO-Vbe) 4/5 (Internal signal) The high-side MOS FET is turned off by the max. duty signal. Preliminary 60 ns (typ ...
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... R2J20751NP Oscillator and Pulse Generator 1. Standalone operation or working as Master Chip in parallel configuration with other chips CLK (IN Max. Duty (Internal signal (typ.) RES (Internal signal) Note: Propagation delay is ignored. Switching frequency for CT 160 A Fsw = 2 (CT( pF) Frequency set range: 200 kHz to 1 MHz R07DS0240EJ0100 Rev ...
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... R2J20751NP Hiccup Operation when the Over-Current Limit (OCL) is Reached TRK-SS 1 Skipped 1024 pulses 0V Note: Propagation delay is ignored. 125% FB Top MOSFET signal Bottom MOSFET signal 2 PGOOD * ON/OFF (UVL) Note: 2. Connected 51 k resistor between PGOOD and VCIN. R07DS0240EJ0100 Rev.1.00 Jan 26, 2011 Detected OCL ...
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... R2J20751NP Applications Multi Phase Operation Tie each CT, CLK and Share pin. Connect OUT pin to IN pin of next switching device. VOUT VCIN R07DS0240EJ0100 Rev.1.00 Jan 26, 2011 REFIN/POS IN EO/C O Device (Master) CLK Share CT OUT REFIN/POS IN EO/C O Device (Slave1) CLK Share CT OUT ...
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... R2J20751NP Multi Phase Operation Waveforms (3 Phase) CLK Device 1 OUT1 (Master) (IN2) The trigger signal is fed back with the same timing as CLK. Device 2 OUT2 (Slave1) (IN3) Device 3 OUT3 (Slave2) (IN1) For the three-phase system, only the master device operates while the voltages on the POS pins of slave devices 1 and 2 are higher than the voltage on the Share pins ...
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... R2J20751NP Phase Control The device incorporates a comparator for control of the phase number. Pulling the voltage on the FB pin up to that on VCIN exchanges the phase control comparator for the error amplifier, and the device operates as a slave. In this case, the output of the comparator (CO) is exchanged for the output of the error amplifier (EO), and the positive input (REFIN) of the error amplifier is exchanged for the positive input (POS) for the comparator ...
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... R2J20751NP Vpos V THR V THF Vshare 2. Selecting the external resistors When the output of phase control comparator becomes low, switching operation of the slave device starts and operation becomes two phase. According to the results of (11) and (12), VTHR and VTHF are 1.473 V and 0.969 V. These become the voltages on the POS pins (comparator non-inverted input pin). VTHR is the start-up level for the slave device and VTHF is the shut-down level for the slave device. We set the output current around 100 ...
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... R2J20751NP Main Characteristics VH vs. Temperature 4.7 4.6 4.5 4.4 4.3 4.2 4.1 4.0 3.9 –50 – Temperature (°C) Viref vs. Temperature 1.90 1.88 1.86 1.84 1.82 1.80 1.78 1.76 1.74 1.72 1.70 –50 – Temperature (°C) R07DS0240EJ0100 Rev.1.00 Jan 26, 2011 4.2 4.1 4.0 3.9 3.8 3.7 3.6 3.5 3.4 75 100 125 150 –50 –25 620 615 610 605 600 595 590 585 580 75 100 125 150 –50 –25 Preliminary VL vs ...
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... R2J20751NP Fsync vs. Temperature 440 430 420 410 400 390 380 370 360 350 –50 – Temperature (°C) Voff vs. Temperature 1.45 1.40 1.35 1.30 1.25 1.20 1.15 1.10 1.05 –50 – Temperature (°C) R07DS0240EJ0100 Rev.1.00 Jan 26, 2011 2.70 2.65 2.60 2.55 2.50 2.45 2.40 2.35 2.30 75 100 125 150 –50 –25 10000 1000 100 75 100 125 150 10 Preliminary Von vs ...
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... JEITA Package Code RENESAS Code — PVQN0040KD HD/2 B Eject pin 1.95 1. Eject pin y1 S Ordering Information Part Name R2J20751NP#G0 R07DS0240EJ0100 Rev.1.00 Jan 26, 2011 Previous Code MASS[Typ.] — 0.07 4-C0.50 1pin 1pin pin indication Quantity ...
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... Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: +60-3-7955-9390, Fax: +60-3-7955-9510 Renesas Electronics Korea Co., Ltd. 11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea Tel: +82-2-558-3737, Fax: +82-2-558-5141 Notice © 2011 Renesas Electronics Corporation. All rights reserved. http://www.renesas.com Colophon 1.0 ...