r2j20751np Renesas Electronics Corporation., r2j20751np Datasheet - Page 10

• Manufacturer Part Number: r2j20751np
• Description: Peak Current Mode Synchronous Buck Controller With Power Mos Fets
• Manufacturer: Renesas Electronics Corporation.

R2J20751NP
Soft Start
TRK-SS pin is provided for start-up setup. Both simple soft start and sequential start up can be realized with this pin
setup. The error amp has two reference inputs and one input for soft start. One of lower voltage inputs of the two
positive inputs is dominant for the amplifier. Therefore simply having CR charging circuit on TRK-SS pin is easier for
soft start design.
The soft start period is determined with the equation as follows when TRK-SS pin has CR charging circuit.
Power Good Indicator
The power good indicator is useful for controlling timing when multiple converter systems are started up or shut down.
Voltage on the FB pin is internally monitored by a power good comparator. The power good comparator compares the
voltage on the pin with 90% of the reference voltage. When the comparator detects the FB voltage reaching the
reference voltage, the Power Good pin becomes high impedance. If the voltage on FB goes over 125% or falls below
80% of the reference voltage, the pin is pulled down to SGND. PGOOD has an n-channel MOS FET operating as an
open drain output and capable of sinking up to 2 mA of current.
Overvoltage Protection
When the output voltage (FB voltage) reaches or exceeds 125% of the reference voltage, switching stops immediately,
the gate of the low-side MOS FET is latched in the high level, which causes shorting of the SW pin to GND. Resetting
to leave the OVP mode is by resupplying VCIN or switching the circuit OFF and ON.
Pre-Overvoltage Protection
When the IC is starting up, an internal circuit monitors the voltage at the switch node and detects the output of
excessive voltages. When a voltage exceeding 1.67 V is detected on the SW pin after release from the UVL state, the
gate of the low-side MOS FET is latched in the high level, which causes shorting of the SW pin to GND. The low-side
MOS FET remains in this state until VCIN is resupplied.
Multi Phase Operation
The R2J20751NP is a scalable solution. Pulling the FB pin of a device up to VCIN causes the device to operate as a
slave. Clock timing is synchronized by connecting the CLK and CT pins of all devices. Current sharing is available by
connecting the Share pins. The timing of switching of the signal on the SW pin is generated from the switching trigger
signal on the IN pin. A device that has received the switching trigger signal outputs the same signal on its OUT pin for
the next device one clock cycle later. The phase number is controllable by the internal phase control comparators of
slave devices.
Slope Compensation
If peak current control leads to the duty cycle being over 50%, sub-harmonic oscillation is generated and the output
voltage becomes unstable regardless of the negative feedback for constant voltage control. The duty cycle, D, is
obtained from the following equation.
To prevent such oscillation, add a constant slope to the slope of the voltage on the CS pin. This added slope is
determined by 10 uA constant current output through the CSLP pin and the value of the connected external capacitor.
Insufficient added slope leads to sub-harmonic oscillation. Too much added slope leads to voltage-mode operation and
poorer response characteristics. An optimal slope (determined by the value of the external capacitor) needs to be set.
The capacitance (Cslp) is determined by the following equation.
In the above equation, Toff is the off portion of the duty cycle (as time), Ipp is the ripple current of the output inductor,
Rcs is the value of the external resistor connected to the CS pin, and M is the rate of the added slope. A capacitor value
that leads to a greater setting of M in the range from 0.5 to 1.0 will lead to a greater added slope.
R07DS0240EJ0100 Rev.1.00
Jan 26, 2011
Tss = –C · R · Ln (1 – REF / VCIN)
REF is REFIN voltage or 0.6 V in internal reference voltage.
D = Vout / VIN  100 (%)
Cslp = 70 A  13700  Toff / (2  Ipp  Rcs  M)
(s)
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Preliminary