l9942 STMicroelectronics, l9942 Datasheet
l9942
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l9942 Summary of contents
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... Order code L9942XP1 L9942XP1TR July 2007 Description The L9942 is an integrated stepper motor driver for bipolar stepper motors with microstepping and programmable current profile look-up-table to allow a flexible adaptation of the stepper motor characteristics and intended operating conditions possible to use different current profiles depending on target criteria: audible noise, vibrations, rotation speed or torque ...
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... Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 4 Functional description of the logic with SPI . . . . . . . . . . . . . . . . . . . . . 21 4.1 Motor stepping clock input (STEP 4.2 PWM output (PWM 4.3 Serial peripheral interface (SPI 2/40 and Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Over- and under voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Reference current output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Charge pump output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Outputs: Qxn (x=A;B n=1; PWM control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 L9942 ...
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... L9942 4.4 Chip select not (CSN 4.5 Serial data in (DI 4.6 Serial data out (DO 4.7 Serial clock (CLK 4.8 Data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5 SPI - Control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1 Control register 5.2 Control register 5.3 Counter and profiles register 5.4 Signal and profile register 5.5 Counter and profile (register 4 and register ...
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... Status register Table 21. Inputs: CSN, CLK, STEP, EN and Table 22. DI timing (see Figure 11 Table 23. Outputs: DO, PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 24. Output: DO timing (see Table 25. CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 26. STEP timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 27. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4/40 Figure 4 and Figure 7 and Figure 13) Figure 12 and Figure 13 L9942 ...
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... L9942 List of figures Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Pin connection (top view Figure 3. Stepping modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 4. Decay modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 5. Thermal data of package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 6. VS monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 7. Logic to set load current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 8. Switching on minimum time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 9. SPI and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 10. Transfer timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 11 ...
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... Note: value of capacitor has choosen carefully to limit the VS voltage below absolute maximum ratings in case of an unexpected QA1 freewheeling condition (e.g. TSD, POR) QA2 Stepper Motor QB1 QB2 QB2 QB2 GNDP GND 24 PGND 23 QA2 RREF 19 VCC 18 TEST 17 GND QB2 13 PGND L9942 ...
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... L9942 Table 2. Pin description Pin Symbol 1, 12, 13, PGND 24 3, 10, 15 QA1, QB1,QB 11 CLK CSN PWM 9 STEP GND 18 TEST 19 VCC Function Power ground: All pins PGND are internally connected to the heat slug. Important: All pins of PGND must be externally connected! Power supply voltage (external reverse protection required): For EMI reason a ceramic capacitor as close as possible to PGND is recommended ...
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... Enable input: The input requires CMOS logic levels. The EN input has a pull-down resistor. In standby-mode outputs will be switched off and all registers will be cleared set to a logic high level then the device will enter the active mode. L9942 ...
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... L9942 2 Device description 2.1 Dual power supply: V The power supply voltage V drive the highside switches. The logic supply voltage V part and the SPI of the device. Due to the independent logic supply voltage the control and status information will not be lost, if there are temporary spikes or glitches on the power supply voltage ...
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... The bridges are switched on until (Figure 4 detail B continuous line triggered by under- (Figure 4 detail B dashed line), that can be detected at LS Figure 3 L9942 (Figure 4 detail A). In fast Micro Stepping DIR=1). If the ...
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... L9942 2.10 Over current detection The overcurrent detection circuit monitors the load current in each activated output stage stage function after detection of current limit during PWM cycle and in LS stage it works permanently. If the load current exceeds the overcurrent detection threshold for at least µ ...
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... Current Driver A Mixed Decay Mode Mixed Decay Slow Decay Mode Mode Slow Decay Current Driver B Mode Slow Decay Mixed Decay Mode Mode L9942 ...
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... L9942 2.13 Decay modes Figure 4. Decay modes Load Current Internal PWM_CLK Detail A: SWITCH ON AND SLOW DECAY Load Current ON T Step Limit Filter time for the purpose of switch off delay in on mode is set by FT register6 FT Cross current protection time is set by SR1 SR0 register0 ...
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... Qxn (x=A;B n=1;2) 1. HBM according to MIL 883C, Method 3015.7 or EIA/JESD22-A114-A 2. HBM with all unzapped pins grounded 14/40 Parameter 400 ms t < max Leaving the limitation of any of these values may cause an irreversible damage of the integrated circuit! Parameter L9942 Value Unit -0 -0.3 to 5 ...
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... L9942 3.3 Thermal data Table 6. Operating junction temperature Symbol T Operating junction temperature j Table 7. Temperature warning and thermal shutdown Symbol Temperature warning T threshold junction jTW ON temperature Temperature warning T threshold junction jTW OFF temperature Thermal shutdown threshold T jSD ON junction temperature Thermal shutdown threshold T jSD OFF ...
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... EN = 5V, CSN=CLK=0V DO changes from high ohmic to logic level LOW = -200 µA, unless otherwise REF Min. Typ. Max -40 ° 125 ° -40 °C 1 125 ° -40 ° 125 ° L9942 Unit mA µ µA 6 µA µA µs ...
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... L9942 3.4.2 Over- and under voltage detection Table 9. Over- and under voltage detection Symbol Parameter V V UV-threshold voltage SUV UV-threshold voltage SUV OFF UV-hysteresis SUV hyst OV-threshold voltage SOV OFF OV-threshold voltage SOV OV-hysteresis SOV hys ...
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... MIN MAX | L9942 Unit Unit mΩ mΩ mΩ mΩ mΩ mΩ ...
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... L9942 Note: Current profile has to pre set with 11111 and load to register 1. Output current limit I value of DAC Phase A/B (bits I0) in register1. Values of DAC Phase A and B can read out and depends on set up done before: 1. direction DIR, stepping mode ST1 ST0 and phase counter register 0 and 2 ...
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... T Filter time of current comparator FT T Cross current protection time CC T Blank time of current comparator Time L9942 Unit kHz kHz µs µs µs µs µs µs µs µs V/µs V/µs V/µs V/µs ...
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... L9942 4 Functional description of the logic with SPI 4.1 Motor stepping clock input (STEP) Rising edge of signal STEP is latched synchronized by internal clock. At next start of a new PWM cycle the new values of output current limit are used to drive motor in next position. Before start new motor step this signal has to be low for at least two internal clock periods to reset latch ...
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... DT1 DT0 PWM Current Profile 2 NPWM Current Profile DT3 DT2 Current Profile DT6 DT5 Read-Only Openload Current Profile 8 Phase Phase Overcurrent HSB1 LSB2 LSB1 HSA2 HSA1 LSA2 LSA1 L9942 ...
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... L9942 5 SPI - Control and status registers 5.1 Control register 0 Table 14. Control register 0 Phase counter Bit Access Reset Name The meaning of the different bits is as follows: : DIR This bit controls direction of motor movement. DIR=1 clockwise DIR=0 counter clockwise. ...
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... DAC phase AI4 AI3 AI2 AI1 Table 12. Current profile L9942 AI0 Table 12 ...
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... L9942 5.4 Signal and profile register 3 Table 17. Signal and profile register 3 Current profile 3 Bit Access Reset Name The meaning of the different bits is as follows These bits are loaded in register1 DAC Phase needed. ...
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... Current profile See also parameter < 250uA), then is RERR=0. REF =2.5us F Overcurrent LSB1 HSA2 HSA1 LSA2 Table 9) Table 7) L9942 Table LSA1 ...
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... L9942 5.8 Auxiliary logic blocks 5.8.1 Fault condition Logical level at pin D0 represents fault condition valid from first high to low edge of signal CLK up to transfer of data bit D12. Fault bit is an logical OR of: Control and Status Register 6 bit 5 and 6 for Open Load, bit7 reference current failure ...
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... V < VCC < 5.3 V (1) and Figure 13) Test condition VCC = 5 V VCC = 5 V VCC = 5 V VCC = 5 V VCC = 5 V VCC = 5 V VCC = 5 V VCC = 5 V =+125°C: SPI communication @4.25MHz j L9942 = -200 μA, unless REF Typ. Max. Unit 0.6*VCC 0.7*VCC 0.1*VCC -50 -25 -10 µ µA ...
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... L9942 6.3 Outputs: DO, PWM Table 23. Outputs: DO, PWM Symbol Parameter V DOoutL output low level V PWMoutL V DOoutH output high level V PWMoutH I tristate leakage current DOoutLK I tristate leakage current PWMoutLK (1) C tristate input capacitance out 6.4 Output: DO timing Table 24. Output: DO timing (see Symbol Parameter t DO rise time ...
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... CLK t CLKH set DI hold Valid Min. Typ CSN_HI,min new data fault bit actual data t set CLK Valid L9942 Max. Unit µs time 0 1 time A2 A1 time time time 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC ...
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... L9942 Figure 12. SPI - DO Valid data delay time and valid time CLK DO (low to high) DO (high to low) Figure 13. DO enable and disable time ...
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... Figure 14. Timing of status bit 0 (fault condition) CSN high to low and CLK stays low: status information of data bit 0 (fault condition) is transferred to D0 CSN CLK D0: status information of data bit 0 (fault condition) will stay as long as CSN is low 32/40 DI: data is not accepted L9942 time time time time ...
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... Load current control and detection of overcurrent (shortages at outputs) The L9942 controls load current in the two full bridges by using a pulls with modulation (PWM) regulator. The mirrored output current of active HS switch is compared with a programmed reference current (e.g. in figure A2 HSA1 and HSB2). Bridge is switched off if current has exceeded the programmed limit value ...
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... After this it is signalized in register 7 as overcurrent in HS switch (e.g. in 34/40 mode 100). On page 12 you can find in the lower part of Figure 17 HSA1). L9942 ...
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... L9942 Figure 15. Stall detection Load Current Rising During High Speed PWM activ detection ...
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... Current Driver A Current Driver STEP Signal HS Current Monitoring (Load control) LIMIT HSA1 - HS1 on I QA1LIM + 1000 QA1 2mA 2mA - + - - + - - + 2mA QA2 I 2mA B - LS2 on OC LSA2 + - LS Current - + Monitoring - (Overcurrent) L9942 I A ...
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... L9942 Figure 17. Reference generation for PWM control (decay) UP/Down PhaseCounter Count 1,2,4,8 STEP A3 Address Calculation Phase A A3=0 A3=1 Adr A[3..0] Adr neg(A[3..0]) Current-Profile Table stored in register2, ...6 Profile Profile Profile Profile Profile ...
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... TYP. MAX. 2.47 0.084 0.097 2.40 0.084 0.094 0 0.075 0 0.003 0.51 0.013 0.020 0.32 0.009 0.012 10.50 0.398 0.413 7.6 0.291 0.299 0.8 0.031 8.8 0.346 0.10 0.004 0.06 0.002 10.50 0.398 0.413 0.40 0.016 0.85 0.022 0.033 10˚ (max) 4.70 0.161 0.185 7.10 0.256 0.279 L9942 ® OUTLINE AND MECHANICAL DATA PowerSSO -24 (Exposed Pad) 7412818 A ...
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... L9942 9 Revision history Table 27. Document revision history Date 10-Nov-2005 04-May-2006 21-Sep-2006 9-Jul-2007 Revision 1 Initial release. Feature list updated. 2 Part numbers updated. Feature list updated. 3 Table 21 on page 28 Updated the order codes (see 4 Changed the status from Preliminary data to Datasheet. Revision history Changes updated ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 40/40 Please Read Carefully: © 2007 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com L9942 ...