W133 Cypress Semiconductor Corp., W133 Datasheet - Page 9

• Manufacturer Part Number: W133
• Description: Spread Spectrum System Frequency Synthesizer
• Manufacturer: Cypress Semiconductor Corp.

PCI Clock Outputs, PCI_F and PCI1:7 (Lump Capacitance Test Load = 30 pF)
REF Clock Outputs, REF0:1 (Lump Capacitance Test Load = 20 pF)
48-MHZ Clock Output (Lump Capacitance Test Load = 20 pF)
Note:
36. PCI clock is CPU/4 for CPU = 133 MHz and CPU/3 for CPU = 100 MHz.
t
t
t
t
t
t
t
t
t
f
Z
f
t
t
t
f
Z
f
f
m/n
t
t
t
f
Z
Parameter
Parameter
Parameter
P
H
L
R
F
D
JC
SK
O
ST
R
F
D
ST
D
R
F
D
ST
o
o
o
Period
High Time
Low Time
Output Rise Edge Rate Measured from 0.4V to 2.4V
Output Fall Edge Rate
Duty Cycle
Jitter, Cycle-to-Cycle
Output Skew
3V66 to PCI Clock
Skew
Frequency Stabilization
from Power-up (cold
start)
AC Output Impedance
Frequency, Actual
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Frequency Stabilization from
Power-up (cold start)
AC Output Impedance
Frequency, Actual
Deviation from 48 MHz
PLL Ratio
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Frequency Stabilization
from Power-up (cold start)
AC Output Impedance
Description
Description
Description
PRELIMINARY
Measured on rising edge at 1.5V
Duration of clock cycle above 2.4V
Duration of clock cycle below 0.4V
Measured from 2.4V to 0.4V
Measured on rising and falling edge at 1.5V
Measured on rising edge at 1.5V. Maximum difference of
cycle time between two adjacent cycles.
Measured on rising edge at 1.5V.
Covers all 3V66/PCI outputs. Measured on rising edge at
1.5V. 3V66 leads PCI output.
Assumes full supply voltage reached within 1 ms from
power-up. Short cycles exist prior to frequency stabilization.
Average value during switching transition. Used for deter-
mining series termination value.
Determined by PLL divider ratio (see m/n below)
(48.008 – 48)/48
(14.31818 MHz x 57/17 = 48.008 MHz)
Measured from 0.4V to 2.4V
Measured from 2.4V to 0.4V
Measured on rising and falling edge at 1.5V
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to fre-
quency stabilization.
Average value during switching transition. Used
for determining series termination value.
Frequency generated by crystal oscillator
Measured from 0.4V to 2.4V
Measured from 2.4V to 0.4V
Measured on rising and falling edge at 1.5V
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Average value during switching transition. Used
for determining series termination value.
Test Condition/Comments
Test Condition/Comments
Test Condition/Comments
9
[36]
Min.
Min.
0.5
0.5
0.5
0.5
45
45
Min. Typ. Max.
1.5
30
12
12
45
1
1
48.008
14.318
57/17
+167
Typ.
Typ.
25
25
15
Max.
Max.
55
55
2
2
3
2
500
500
2
3
55
4
4
4
3
W133
MHz
V/ns
V/ns
Unit
ppm
V/ns
V/ns
Unit
ms
Unit
V/ns
V/ns
ms
%
%
ms
ns
ns
ns
ps
ps
ns
%