tmp86fp24 TOSHIBA Semiconductor CORPORATION, tmp86fp24 Datasheet - Page 20

• Manufacturer Part Number: tmp86fp24
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

1.4.4
Operating Mode Control
(1) STOP mode
key-on wakeup input (STOP0 to STOP4) which is controlled by the STOP mode release
control register (STOPCR).
5) pin.
following status is maintained.
which can be selected with the SYSCR1<RELM>. Do not use any STOPx (x: 0 to 4) pin
input for releasing STOP mode in edge-sensitive mode.
for stabilizing of the power supply of flash control circuit is executed after the STOP
warm-up time.
Note 1: The STOP mode can be released by either the STOP or key-on wakeup pin
Note 2: During STOP period (from start of STOP mode to end of warm up), due to changes
a.
b.
c.
d. The program counter holds the address 2 ahead of the instruction (e.g., [SET
a.
STOP mode is controlled by the system control register 1, the
The
STOP mode is started by setting SYSCR1<STOP> to “1”. During STOP mode, the
STOP mode includes a level-sensitive mode and an edge-sensitive mode, either of
When the STOP mode is started with the EEPCR<MNPWDW>
(SYSCR1).7]) which started STOP mode.
Oscillations are turned off, and all internal operations are halted.
The data memory, registers, the program status word and port output latches are
all held in the status in effect before STOP mode was entered.
The prescaler and the divider of the timing generator are cleared to “0”.
Level-sensitive release mode (RELM = “1”)
the STOPx (x: 0 to 4) pin input which is enabled by STOPCR. This mode is used
for capacitor backup when the main power supply is cut off and long term battery
backup.
mode will not place in STOP mode but instead will immediately start the release
sequence (warm up). Thus, to start STOP mode in the level-sensitive release mode,
it is necessary for the program to first confirm that the
following two methods can be used for confirmation.
In this mode, STOP mode is released by setting the
When the
STOP
a.
b.
(STOP0 to STOP4). However, because the
wakeup and can not inhibit the release input, the
releasing STOP mode.
in the external interrupt pin signal, interrupt latches may be set to “1” and interrupts
may be accepted immediately after STOP mode is released. Before starting STOP
mode, therefore, disable interrupts. Also, before enabling interrupts after STOP
mode is released, clear unnecessary interrupt latches.
Testing a port P20.
Using an external interrupt input
input).
pin is also used both as a port P20 and an
STOP
pin input is high, executing an instruction which starts STOP
86FP24-18
INT5
STOP
(
INT5
INT5
pin is different from the key-on
STOP
STOP
is a falling edge-sensitive
STOP
(External interrupt input
pin must be used for
STOP
pin input is low. The
pin high or setting
“1”, the CPU wait
pin input and
TMP86FP24
2007-08-24