tmp88ch40img TOSHIBA Semiconductor CORPORATION, tmp88ch40img Datasheet - Page 5

• Manufacturer Part Number: tmp88ch40img
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

2. Functional Description
3. Interrupt Control Circuit
4. Special Function Register
TMP88CH40IMG
1.1
1.2
1.3
1.4
2.1
3.1
3.2
3.3
3.4
3.5
4.1
4.2
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
3.2.1
3.2.2
3.3.1
3.3.2
3.3.3
3.4.1
3.4.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Names and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functions of the CPU Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.4.1
2.1.4.2
2.1.4.3
2.1.4.4
2.1.5.1
2.1.5.2
2.1.5.3
2.1.5.4
Interrupt latches (IL38 to IL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Interrupt enable register (EIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3.2.1
3.3.2.2
3.3.2.3
3.3.2.4
Software Interrupt (INTSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
DBR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Memory Address Map............................................................................................................................... 7
Program Memory (ROM) .......................................................................................................................... 8
Data Memory (RAM) ................................................................................................................................. 8
System Clock Control Circuit .................................................................................................................... 9
Reset Circuit ........................................................................................................................................... 17
Interrupt master enable flag (IMF) .......................................................................................................... 21
Individual interrupt enable flags (EF38 to EF3) ...................................................................................... 21
Interrupt acceptance processing is packaged as follows........................................................................ 24
Saving/restoring general-purpose registers ............................................................................................ 25
Interrupt return ........................................................................................................................................ 27
Address error detection .......................................................................................................................... 28
Debugging .............................................................................................................................................. 28
Clock Generator
Timing Generator
Standby Control Circuit
Controlling Operation Modes
External Reset Input
Adress Trap Reset
Watchdog Timer Reset
System Clock Reset
Using Automatic register bank switcing
Using register bank switching
Using PUSH and POP instructions
Using data transfer instructions
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