tmp88f846ug TOSHIBA Semiconductor CORPORATION, tmp88f846ug Datasheet - Page 51
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tmp88f846ug
Manufacturer Part Number
tmp88f846ug
Description
8 Bit Microcontroller
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP88F846UG.pdf
(244 pages)
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5. Input/Output Ports
have a latch, so it is desirable that the input data be retained externally until it is read out, or read several times before
being processed. Figure 5-1 shows input/output timing.
cution. Because this timing cannot be recognized from the outside, transient input data such as chattering needs to be
dealt with in a program. The timing at which data is forwarded to input/output ports is S2 state in the write cycle of
instruction execution.
The TMP88F846UG contains 5 input/output ports comprised of 33 pins.
All output ports contain a latch, and the output data therefore are retained by the latch. But none of the input ports
The timing at which external data is read in from input/output ports is S1 state in the read cycle of instruction exe-
Note: The read/write cycle positions vary depending on instructions.
Port P1
Port P2
Port P3
Port P4
Port P6
Data input
Output latch pulse
Data output
execution cycle
execution cycle
nput strobe
nstruction
nstruction
Primary Function
Figure 5-1 Example of Input/Output Timing
6-bit I/O port
3-bit I/O port
8-bit I/O port
8-bit I/O port
8-bit I/O port
S0
S0
Fetch cycle
Fetch cycle
External interrupt input, Timer/counter input/output, divider output
External interrupt input, Timer/counter input/output, STOP mode release
signal input
Motor control input/output
Timer/counter output, Serial interface input/output, motor control circuit
input, Serial PROM mode control input
Analog input and motor control circuit output
S1
S1
S2
S2
S3
S3
Page 41
Example: LD A, (x)
Example: LD (x), A
S0
S0
(b) Output timing
(a) nput timing
Fetch cycle
Fetch cycle
S1
S1
Secondary Functions
S2
S2
S3
S3
S0
S0
Read cycle
Write cycle
S1
S1
S2
S2
S3
S3
TMP88F846UG
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