tmp89fm46a TOSHIBA Semiconductor CORPORATION, tmp89fm46a Datasheet - Page 36

• Manufacturer Part Number: tmp89fm46a
• Description: Tlcs-870/c1 Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

RA000
System control register 1
System control register 2
(0x0FDC)
(0x0FDD)
SYSCR1
SYSCR2
Note 1: fosc: Internal high-frequency clock [Hz], fc: External high-frequency clock [Hz], fcgck: Gear clock [Hz], fs: External low-
Note 2: Bits 2, 1 and 0 of SYSCR1 are read as "0".
Note 3: If the STOP mode is activated with SYSCR1<OUTEN> set at "0", the port internal input is fixed to "0". Therefore, an
Note 4: The P11 pin is also used as the STOP pin. When the STOP mode is activated, the pin reverts to high impedance state
Note 5: Writing of the second byte data will be executed improperly if the operation is switched to the STOP state by an instruction,
Note 6: Don't set SYSCK1<DV9CK> to "1" before the oscillation of the external low-frequency clock oscillation circuit becomes
Note 7: In the SLOW1/2 or SLEEP1 mode, fs/4 is input to stage 9 of the divider, regardless of the state of SYSCR1< DV9CK >.
Note 8: SYSCR1<OSCSEL> should be set while SYSCR2<SYSCK> is "0" (during the NORMAL1 or NORMAL2 mode). Writing
OSCSEL
TGHALT
OUTEN
OSCEN
Read/Write
DV9CK
Read/Write
SYSCK
Bit Symbol
Bit Symbol
After reset
frequency clock [Hz]
external interrupt may be set at the falling edge, depending on the pin state when the STOP mode is activated.
and is put in input mode, regardless of the state of SYSCR1<OUTEN>.
such as LDW, which executes 2-byte data transfer at a time.
stable.
to SYSCR1<OSCSEL> while SYSCR2<SYSCK> = "1" (during the SLOW1 or SLOW2 mode) has no effect.
After reset
RELM
STOP
XTEN
IDLE
XEN
Activates the STOP mode
Selects the STOP mode release
method
Selects the port output state in the
STOP mode
Selects the input clock to stage 9 of
the divider
Selects the high-frequency refer-
ence clock (fh)
Controls the internal high-frequency
clock (fosc)
Controls the external high-frequency
clock (fc)
Controls the external low-frequency
clock (fs)
Selects a system clock
CPU and WDT control
(IDLE1/2 or SLEEP1 mode)
TG control
(IDLE0 or SLEEP0 mode)
OSCEN
STOP
R/W
R/W
7
0
7
1
RELM
XEN
R/W
R/W
6
0
6
0
OUTEN
XTEN
R/W
R/W
5
0
5
0
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0 :
1 :
0 :
1 :
0 :
1 :
0 :
1 :
0 :
1 :
0 :
1 :
0 :
1 :
0 :
1 :
0 :
1 :
0 :
1 :
0 :
1 :
Operate the CPU and the peripheral circuits
Stop the CPU and the peripheral circuits (activate the STOP mode)
Edge-sensitive release mode (Release the STOP mode at the rising edge
of the STOP mode release signal)
Level-sensitive release mode (Release the STOP mode at the "H" level of
the STOP mode release signal)
High impedance
Output hold
fcgck/2
fs/4
Internal high-frequency clock (fosc)
External high-frequency clock (fc)
Stop oscillation
Continue or start oscillation
Stop oscillation
Continue or start oscillation
Stop oscillation
Continue or start oscillation
Gear clock (fcgck) (NORMAL1/2 or IDLE1/2 mode)
External low-frequency clock (fs/4) (SLOW1/2 or SLEEP1 mode)
Operate the CPU and the WDT
Stop the CPU and the WDT (Activate IDLE1/2 or SLEEP1 mode)
Enable the clock supply from the TG to all the peripheral circuits
Disable the clock supply from the TG to the peripheral circuits except the
TBT (Activate IDLE0 or SLEEP0 mode)
SYSCK
DV9CK
R/W
R/W
9
4
0
4
0
OSCSEL
IDLE
R/W
R/W
3
0
3
0
TGHALT
R/W
R
2
0
2
0
-
R
1
0
1
R
0
-
-
TMP89FM46A
R
R
0
0
0
0
-
-