W83193R Winbond Electronics Corp America, W83193R Datasheet
W83193R
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W83193R Summary of contents
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... Winbond for any damages resulting from such improper use or sales 83.MHZ 3-DIMM CLOCK W83193R-02/-04/-04A Data Sheet Revision History Version On Web n.a. All of the versions before 0.50 are for internal use. 1.0 Change version and version on web site to 1.0 W83193R-02/-04/-04A Main Contents Publication Release Date: Nov. 1998 Revision 1.0 ...
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... The W83193R-02/-04/-04A also provides I disable each clock outputs and choose the 0.5% or 1.5% center type spread spectrum. The W83193R-02/-04/-04A accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. High drive PCI and SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as maintaining 50± ...
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BLOCK DIAGRAM Xin Xout FS(0:2)* MODE* CPU3.3#_2.5* CPU_STOP# PCI_STOP# SDATA SCLK 4.0 PIN CONFIGURATION REF0/CPU3.3#_2.5 Xout Vddq3 PCICLK_F/*FS1 PCICLK0/*FS2 PCICLK1 PCICLK2 PCICLK3 PCICLK4 Vddq3 PCICLK5/PCI_STOP# SDRAM11 SDRAM10 Vddq3 SDRAM 9 SDRAM 8 SDATA SDCLK - 3 - PLL2 1/2 ...
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PIN DESCRIPTION IN - Input OUT - Output I/O - Bi-directional Pin # - Active Low * - Internal 250kΩ pull-up 5.1 Crystal I/O SYMBOL PIN Xin Xout 5.2 CPU, SDRAM, PCI Clock Outputs SYMBOL PIN CPUCLK [ 0:3 ...
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I C Control Interface SYMBOL PIN SDATA SDCLK 5.4 Fixed Frequency Outputs SYMBOL PIN REF0 / CPU3.3#_2.5 REF1 / CPU_STOP# 24MHz / *MODE 48MHz / *FS0 5.5 Power Pins SYMBOL Vdd Vddq2 Vddq2b Vddq3 6,14,19, 30, 36 Vss ...
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... FREQUENCY SELECTION W83193R-02/-04 frequency table FS2 FS1 FS0 W83193R-04A frequency table FS2 FS1 FS0 7.0 CPU 3.3#_2.5 BUFFER SELECTION CPU 3 ...
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... MODE=1, these functions are not available. A particular clock could be enabled as both the 2-wire serial control interface and one of these pins indicate that it should be enable. The W83193R-02/-04/-04A may be disabled in the low state according to the following table in order to reduce power consumption. All clocks are stopped in the low state, but maintain a valid high period on transitions from running to stop ...
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Bytes sequence order for I C controller : Clock Address 8 bits dummy Ack A(6:0) & R/W Command code Set R when ?ead back” ,the data sequence is as follows : Clock Address Ack A(6:0) & R/W ...
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Frequency table selection by software via I SSEL2 SSEL1 SSEL0 FUNCTION TABLE Function CPU Description Hi-Z ...
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Register 2: PCI Clock Register (1 = enable Stopped) Bit @PowerUp Pin 8.3.4 ...
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Register 5: Peripheral Control (1 = enable Stopped) Bit @PowerUp Pin 8.3.7 Register ...
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SPECIFICATIONS 9.1 ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. ...
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DC CHARACTERISTICS ± Vdd = Vddq3 = 3. Vddq2 = Vddq2b = 2.375V~2. Parameter Symbol Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Voltage ...
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BUFFER CHARACTERISTICS 9.4.1 TYPE 1 BUFFER FOR CPU (0:3) Parameter Symbol Pull-Up Current Min I Pull-Up Current Max I Pull-Down Current Min I Pull-Down Current Max Rise/Fall Time Min T Between 0.4 V and 2.0 V Rise/Fall Time Max ...
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TYPE 3 BUFFER FOR REF1, 24MHZ, 48MHZ Parameter Symbol Pull-Up Current Min I OH(min) Pull-Up Current Max I OH(max) Pull-Down Current Min I OL(min) Pull-Down Current Max I Rise/Fall Time Min T Between 0.8 V and 2.0 V Rise/Fall ...
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POWER MANAGEMENT TIMING 10.1 CPU_STOP# Timing Diagram ( synchronous ) CPUCLK (Internal) PCICLK (Internal) PCICLK_F CPU_STOP# CPUCLK[0:3] SDRAM For synchronous Chipset, CPU_STOP# pin is a synchronous “ active low ” input pin used to stop the CPU clocks for ...
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OPERATION OF DUAL FUCTION PINS Pins 25, and 26 are dual function pins and are used for selecting different functions in this device (see Pin description). During power up, these pins are in input mode (see ...
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Vdd Series Ω 10k Terminating Resistor Device Pin Ω 10k Ground Programming Header Vdd Pad Ground Pad Series 10kΩ Terminating Resistor Device Pin - 18 - Clock Trace EMI Reducing Cap Optional Ground Clock Trace EMI Reducin gCap Optional Ground ...
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... Ferrite Bead? (FB) are recommended to further reduce the power supply noise. 5.The power supply race to the Vdd pins must be thick enough so that voltage drops across the trace resistance is negligible. FB1 Vdd Vdd Plane (3.3V) C1 C31 C32 C33 C34 - 19 - W83193R-02/-04/-04A Vdd2 Plane ...
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... W83193R-02/-04 14.0 HOW TO READ THE TOP MARKING W83193R-02 28051234 814GBB 1st line: Winbond logo and the type number: W83193R-02/-04 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 814: packages made in '98, week 14 G: assembly house ID ...
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PACKAGE DRAWING AND DIMENSIONS Headquarters No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/ Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd. Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 TLX: 16485 ...