uaa2068g NXP Semiconductors, uaa2068g Datasheet - Page 7

• Manufacturer Part Number: uaa2068g
• Description: Transmit Chain And Synthesizer With Integrated Vco For Dect
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Synthesizer
M
The main divider is clocked by the RF signal from the
internal frequency doubler. The divider operates at
frequencies from 1880 to 1920 MHz. It consists of a
bipolar prescaler followed by a CMOS counter. Any main
divider ratio from 1024 to 1151 inclusive can be
programmed.
R
The reference divider is clocked by the signal at pin XTAL.
The circuit operates with levels from 50 to 500 mV (RMS)
at a frequency of 13.824 MHz, with a fixed divider ratio
of 8.
P
The phase comparator is driven by the output of the main
and reference dividers. It produces current pulses at
pin CP. The pulse duration is equal to the difference in
time of arrival of the edges from the two dividers. If the
main divider edge arrives first, CP sinks current. If the
reference divider edge arrives first, CP sources current.
The DC value of the charge-pump current is nominally ten
times the current drawn by the external resistor connected
to pin R
the gain of the phase detector remains linear even for
small phase errors.
The charge pump has a separate supply, V
helps to reduce the interference on the charge-pump
output from other parts of the circuit. V
than the other supply voltages if a wider range on the VCO
input is required. The V
than that on other V
Serial programming bus
A simple 3-line unidirectional serial bus is used to program
the circuit. These 3 lines are data (DATA), clock (CLK) and
enable (S_EN). The data sent to the device is loaded in
bursts framed by S_EN. Programming clock edges and
their appropriate data bits are ignored until S_EN goes
active LOW. The programmed information is read directly
by the main divider when S_EN returns HIGH. During
synthesizer operation, S_EN should be kept HIGH.
In normal operating mode, only the last 8 bits serially
clocked into the device are retained within the register.
Additional leading bits are ignored, and no check is made
on the number of clock pulses. The data format is shown
in Table 2. The first bit entered is b7, the last bit is b0.
1998 Nov 19
HASE COMPARATOR
EFERENCE DIVIDER
AIN DIVIDER
Transmit chain and synthesizer with
integrated VCO for DECT
SET
. Additional circuitry is included to ensure that
CC
pins.
CC(CP)
voltage must not be less
CC(CP)
CC(CP)
can be higher
, which
7
For the divider ratio, the first bit (b6) entered is the most
significant (MSB).
S_EN must be LOW to capture new programming data.
S_EN must be HIGH to switch on the synthesizer.
Operating modes
The synthesizer is on when the input signal S_EN is HIGH,
and off when S_EN is LOW. When turned on, the dividers
and phase detector are synchronized to avoid a random
initial phase error. When turned off, the phase detector is
synchronized with the dividers to avoid interrupting a
charge-pump pulse.
The VCO is on when the input signal VCO_ON is HIGH.
The polarity of VCO_ON is chosen for compatibility with
output S_PWR at the ABC chip. When turned on, it needs
some time (typically 30 s) to reach its steady state.
The TX preamplifier is on when both R_OFF and VCO_ON
are HIGH. The polarity of R_OFF is chosen for
compatibility with output R_PWR at the ABC chip. When
turned on, it needs some time (typically 10 s) to reach its
steady state. In transmit mode, the timing of the R_OFF
LOW-to-HIGH transition can be chosen such that the TX
preamplifier is turned on while the synthesizer loop
remains closed thus avoiding frequency pulling of the
VCO. In the receive mode, depending on the exact timing
of R_OFF compared to VCO_ON, the TX preamplifier can
be switched on at the beginning of the previous slot, but is
switched off when the R_OFF goes LOW; this occurs
when the synthesizer loop is closed. The LO output
amplifier is turned on when R_OFF is LOW and VCO_ON
is HIGH.
The UAA2068G has a very low current consumption in
power-down mode.
Product specification
UAA2068G