lp8765rlx National Semiconductor Corporation, lp8765rlx Datasheet - Page 26

• Manufacturer Part Number: lp8765rlx
• Description: High Performance Power Management Unit For Handset Applications
• Manufacturer: National Semiconductor Corporation

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I
INTERFACE BUS OVERVIEW
The I
cess to the programmable functions and registers on the
device.
This protocol uses a two-wire interface for bi-directional com-
munications between the ICs connected to the bus. The two
interface lines are the Serial Data Line (SDA), and the Serial
Clock Line (SCL). These lines should be connected to a pos-
itive supply, via a pull-up resistor of 1.5 kΩ and remain HIGH
even when the bus is idle.
Every device on the bus is assigned a unique address and
acts as either a Master or a Slave depending on whether it
generates or receives the SCL.
DATA TRANSACTIONS
One data bit is transferred during each clock pulse. Data is
sampled during the high state of the SCL. Consequently,
throughout the clock’s high period, the data should remain
stable. Any changes on the SDA line during the high state of
the SCL and in the middle of a transaction, aborts the current
transaction. New data should be sent during the low SCL
state. This protocol permits a single data line to transfer both
command/control information and data using the syn-
chronous serial clock.
Each data transaction is composed of a Start Condition, a
number of byte transfers (set by the software) and a Stop
2
C-Compatible Serial Bus Interface
2
C-compatible synchronous serial interface provides ac-
FIGURE 3. Bit Transfer
FIGURE 5. Bus Acknowledge Cycle
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Condition to terminate the transaction. Every byte written to
the SDA bus must be 8 bits long and is transferred with the
most significant bit first. After each byte, an Acknowledge sig-
nal must follow. The following sections provide further details
of this process.
START AND STOP
The Master device on the bus always generates the Start-
and-Stop Conditions (control codes). After a Start Condition
is generated, the bus is considered busy, and it retains this
status until a certain time after a Stop Condition is generated.
A high-to-low transition of the data line (SDA) while the clock
(SCL) is high indicates a Start Condition. A low-to-high tran-
sition of the SDA line while the SCL is high indicates a Stop
Condition.
In addition to the first Start Condition, a repeated Start Con-
dition can be generated in the middle of a transaction. This
allows another device to be accessed, or a register read cycle.
ACKNOWLEDGE CYCLE
The Acknowledge Cycle consists of two signals: the acknowl-
edge clock pulse the master sends with each byte transferred,
and the acknowledge signal sent by the receiving device. The
master generates the acknowledge clock pulse on the ninth
clock pulse of the byte transfer. The transmitter releases the
SDA line (permits it to go high) to allow the receiver to send
the acknowledge signal. The receiver must pull down the SDA
line during the acknowledge clock pulse and ensure that SDA
remains low during the high period of the clock pulse, thus
signaling the correct reception of the last data byte and its
readiness to receive the next byte.
FIGURE 4. Start-and-Stop Conditions
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